Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches TSSOP 16

High Voltage Latch-Up Proof,

Quad SPST Switches

ADG5412/ADG5413

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Latch-up proof

8 kV human body model (HBM) ESD rating

Low on resistance (<10 Ω)

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

APPLICATIONS

Relay replacement

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

IN4

ADG5412

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

IN2

IN3

IN1

IN4

ADG5413

09202-001

Figure 1.

GENERAL DESCRIPTION

The ADG5412/ADG5413 contain four independent single-

pole/single-throw (SPST) switches. The ADG5412 switches

turn on with Logic 1. The ADG5413 has two switches with

digital control logic similar to that of the ADG5412; however,

the logic is inverted on the other two switches. Each switch

conducts equally well in both directions when on, and each

switch has an input signal range that extends to the supplies.

In the off condition, signal levels up to the supplies are blocked.

The ADG5412 and ADG5413 do not have a V

pin. The digital

inputs are compatible with 3 V logic inputs over the full

operating supply range.

The on-resistance profile is very flat over the full analog input

range, which ensures good linearity and low distortion when

switching audio signals. High switching speed also makes the

devices suitable for video signal switching. The ADG5413

exhibits break-before-make switching action for use in

multiplexer applications.

PRODUCT HIGHLIGHTS

1. Trench isolation guards against latch-up. A dielectric trench

separates the P and N channel transistors thereby preventing

latch-up even under severe overvoltage conditions.

2. Low R

3. Dual-supply operation. For applications where the analog

signal is bipolar, the ADG5412/ADG5413 can be operated

from dual supplies up to ±22 V.

4. Single-supply operation. For applications where the analog

signal is unipolar, the ADG5412/ADG5413 can be operated

from a single rail power supply up to 40 V.

5. 3 V logic compatible digital inputs: V

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

logic power supply required.

Summary of content (20 pages)

PAGE 1
High Voltage Latch-Up Proof, Quad SPST Switches ADG5412/ADG5413 FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 8 kV human body model (HBM) ESD rating Low on resistance (<10 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range S1 D1 S2 S2 IN2 IN2 D2 ADG5412 D2 ADG5413 S3 IN3 S3 IN3 D3 D3 S4 Relay replacement Automatic test equipment Data acquisition Instrumentation Avio
PAGE 2
ADG5412/ADG5413 TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx..............................7 Applications....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagrams............................................................. 1 ESD Caution......
PAGE 3
ADG5412/ADG5413 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C −40°C to +125°C Unit VDD to VSS V Ω typ 9.8 14 16 Ω max Ω typ 0.7 1.2 1.6 0.9 1.1 VS = ±10 V, IS = −10 mA 2 2.2 Ω max Ω typ Ω max nA typ VDD = +16.5 V, VSS = −16.
PAGE 4
ADG5412/ADG5413 Parameter POWER REQUIREMENTS IDD 25°C −40°C to +85°C 45 55 0.001 ISS Unit μA typ μA max μA typ μA max V min/V max 70 1 ±9/±22 VDD/VSS 1 −40°C to +125°C Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2.
PAGE 5
ADG5412/ADG5413 Parameter Total Harmonic Distortion + Noise 25°C 0.007 −40°C to +85°C Unit % typ −3 dB Bandwidth 160 MHz typ Insertion Loss −0.6 dB typ 17 17 60 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS 50 70 0.
PAGE 6
ADG5412/ADG5413 Parameter Break-Before-Make Time Delay, tD (ADG5413 Only) 25°C 70 −40°C to +85°C Unit ns typ Test Conditions/Comments RL = 300 Ω, CL = 35 pF 38 VS1 = VS2 = 8 V; see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MH
PAGE 7
ADG5412/ADG5413 Parameter DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 2.0 0.
PAGE 8
ADG5412/ADG5413 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.
PAGE 9
ADG5412/ADG5413 VSS 2 TOP VIEW 12 NC (Not to Scale) S4 6 11 S3 GND 5 D3 IN4 8 9 IN3 NC = NO CONNECT S4 4 12 S2 ADG5412/ ADG5413 11 VDD TOP VIEW (Not to Scale) 9 S3 D4 5 10 GND 3 09202-002 D4 7 PIN 1 INDICATOR S1 1 10 NC NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. 09202-003 VDD ADG5412/ ADG5413 14 IN2 S2 13 VSS 4 13 D2 14 D3 8 D2 S1 3 15 IN1 IN2 15 IN3 7 16 D1 2 IN4 6 IN1 1 16 D1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3.
PAGE 10
ADG5412/ADG5413 TYPICAL PERFORMANCE CHARACTERISTICS 16 14 ON RESISTANCE (Ω) 10 8 VDD10 = +13.5V VSS = –13.5V 6 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V TA = 25°C 10 VDD = +11V VSS = –11V 12 ON RESISTANCE (Ω) 12 VDD = +10V VDD = +9V VSS = –10V VSS = –9V TA = 25°C VDD = 36V VSS = 0V VDD = 32.4V VSS = 0V 8 6 VDD = 39.
PAGE 11
ADG5412/ADG5413 30 0.8 VDD = 12V VSS = 0V LEAKAGE CURRENT (nA) 25 ON RESISTANCE (Ω) VDD = +20V VSS = –20V VBIAS = +15V/–15V 0.6 TA = +125°C 20 TA = +85°C 15 TA = +25°C TA = –40°C 10 5 ID, IS (ON) + + ID, IS (ON) – – 0.4 IS (OFF) + – 0.2 ID (OFF) – + 0 –0.2 IS (OFF) – + –0.4 2 4 6 8 10 09202-042 12 VS, VD (V) 0 0.6 8 TA = +25°C 6 TA = –40°C LEAKAGE CURRENT (nA) 4 2 0 10 5 15 20 30 25 35 40 VS, VD (V) 0.
PAGE 12
ADG5412/ADG5413 –10 –20 –30 –30 ACPSRR (dB) –20 –60 NO DECOUPLING CAPACITORS –40 –50 –60 –70 –70 –80 –80 DECOUPLING CAPACITORS –90 –90 –100 1k –100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 10k 0.10 TA = 25°C VDD = +15V VSS = –15V –30 0.07 –40 0.06 THD + N (%) 0.08 –50 –60 –80 0.02 –90 0.01 10M 100M 1G FREQUENCY (Hz) 0 5 10 15 TA = 25°C VDD = +15V VSS = –15V –0.5 400 –1.
PAGE 13
ADG5412/ADG5413 350 300 tON (12V) tON (±20V) tON (±15V) 200 tOFF (±15V) tON (36V) 150 100 tOFF (12V) tOFF (36V) tOFF (±20V) 50 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 09202-031 TIME (ns) 250 Figure 22. tON, tOFF Times vs. Temperature Rev.
PAGE 14
ADG5412/ADG5413 TEST CIRCUITS IS (OFF) Dx Sx Dx ID (OFF) A A VD VS VD Figure 23. On Leakage 09202-015 VS 09202-016 Sx A ID (ON) Figure 27. Off Leakage VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS IDS RS Sx INx VS V p-p V1 Dx 09202-014 09202-024 GND VS RON = V1/IDS Figure 24. On Resistance VDD Figure 28. THD + Noise VSS VDD 0.1µF 0.1µF VSS 0.1µF 0.
PAGE 15
ADG5412/ADG5413 VDD VSS VSS D1 S2 D2 CL 35pF RL 300Ω CL 35pF VOUT2 ADG5413 90% 90% 0V 90% 90% 0V GND tD tD Figure 30. Break-Before-Make Time Delay, tD VDD VSS 0.1µF 0.1µF VIN VDD Sx VS ADG5412 50% 50% VSS VOUT Dx CL 35pF RL 300Ω INx 90% VOUT 90% GND tOFF tON 09202-018 IN1, IN2 RL 300Ω VOUT2 VOUT1 50% Figure 31. Switching Times RS VS VDD VSS VDD VSS Sx Dx VOUT VIN ADG5412 ON OFF CL 1nF IN VOUT QINJ = CL × ∆VOUT GND Figure 32. Charge Injection Rev.
PAGE 16
ADG5412/ADG5413 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN is the digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay between applying the digital control input and the output switching on. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. ΔRON ΔRON represents the difference between the RON of any two channels.
PAGE 17
ADG5412/ADG5413 TRENCH ISOLATION In the ADG5412 and ADG5413, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 33. Trench Isolation Rev.
PAGE 18
ADG5412/ADG5413 APPLICATIONS INFORMATION The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5412/ADG5413 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V.
PAGE 19
ADG5412/ADG5413 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.