Datasheet

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High Voltage Latch-Up Proof,

Dual SPDT Switches

Data Sheet

ADG5236

Rev. B Document Feedback

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FEATURES

Latch-up immune under all circumstances

2.5 pF off source capacitance

12 pF off drain capacitance

−0.6 pC charge injection

Low leakage: 0.4 nA maximum at 85°C

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

APPLICATIONS

High voltage signal routing

Automatic test equipment

Analog front-end circuits

Precision data acquisition

Industrial instrumentation

Amplifier gain select

Relay replacement

FUNCTIONAL BLOCK DIAGRAMS

ADG5236

S1A

S1B

IN1

S2A

S2B

IN2

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

09769-001

Figure 1. TSSOP Package

ADG5236

S2A

S2B

S1A

S1B

IN2 ENIN1

LOGIC

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

09769-002

Figure 2. LFCSP Package

GENERAL DESCRIPTION

The ADG5236 is a monolithic CMOS device containing two

independently selectable single-pole/double throw (SPDT)

switches. An EN input on the LFCSP package enables or

disables the device. When disabled, all channels switch off. Each

switch conducts equally well in both directions when on and

has an input signal range that extends to the supplies. In the off

condition, signal levels up to the supplies are blocked. Both

switches exhibit break-before-make switching action for use in

multiplexer applications.

The ultralow capacitance and charge injection of these switches

make them ideal solutions for data acquisition and sample-and-

hold applications, where low glitch and fast settling are required.

Fast switching speed together with high signal bandwidth make

the device suitable for video signal switching.

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel

transistors thereby preventing latch-up even under severe

overvoltage conditions.

2. Ultralow Capacitance and <1 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5236 can be operated from dual supplies up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5236 can be operated from a single rail power supply

up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

Logic Power Supply Required.

Summary of content (20 pages)

PAGE 1
High Voltage Latch-Up Proof, Dual SPDT Switches ADG5236 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up immune under all circumstances 2.5 pF off source capacitance 12 pF off drain capacitance −0.6 pC charge injection Low leakage: 0.
PAGE 2
ADG5236 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 Functional Block Diagrams ...................................................
PAGE 3
Data Sheet ADG5236 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 160 200 1.4 8 38 50 0.01 0.1 0.01 0.1 0.02 0.
PAGE 4
ADG5236 Parameter POWER REQUIREMENTS IDD ISS Data Sheet 25°C −40°C to +85°C 45 55 0.001 −40°C to +125°C 70 1 VDD/VSS 1 ±9/±22 Unit µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2.
PAGE 5
Data Sheet Parameter CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS ADG5236 25°C 2.5 12 15 −40°C to +85°C 50 70 0.
PAGE 6
ADG5236 Parameter Off Isolation Data Sheet 25°C −90 −40°C to +85°C −40°C to +125°C Channel-to-Channel Crosstalk −90 dB typ −3 dB Bandwidth Insertion Loss 185 −11 MHz typ dB typ 3 16 16 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 40 9/40 µA typ µA max V min/V max −40°C to +125°C Unit 0 V to VDD V max Ω typ 65 VDD 1 Unit dB typ Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 26 RL =
PAGE 7
Data Sheet Parameter tOFF ADG5236 Break-Before-Make Time Delay, tD 25°C 170 215 75 −40°C to +85°C −40°C to +125°C Charge Injection, QINJ −0.6 Unit ns typ ns max ns typ ns min pC typ 215 225 Off Isolation −85 dB typ Channel-to-Channel Crosstalk −85 dB typ −3 dB Bandwidth Insertion Loss 266 −7 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 2.
PAGE 8
ADG5236 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, SxA, SxB, or Dx Pin Continuous Current, SxA, SxB, or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP Reflow Soldering Peak Temperature, Pb Free 1 2 Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.
PAGE 9
Data Sheet ADG5236 D1 1 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B 13 D2 NC 7 10 S2A NC 8 9 IN2 NC = NO CONNECT ADG5236 11 VDD VSS 3 TOP VIEW (Not to Scale) 10 S2B GND 4 9 D2 NC 5 11 09769-003 GND 6 12 EN S1B 2 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. Figure 3. TSSOP Pin Configuration 09769-004 ADG5236 14 NC NC S1B 4 13 NC 14 NC 7 NC D1 3 S2A 8 NC 15 16 S1A 16 IN2 6 IN1 1 S1A 2 15 IN1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4.
PAGE 10
ADG5236 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 160 TA = 25°C TA = 25°C 140 VDD = +18V VSS = –18V 120 ON RESISTANCE (Ω) 120 100 VDD = +20V VSS = –20V 80 VDD = +22V VSS = –22V 60 100 60 40 20 20 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) 0 0 5 10 15 20 25 30 35 40 VS, VD (V) Figure 5. On Resistance vs. VS, VD (Dual Supply) 250 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 80 40 09769-105 ON RESISTANCE (Ω) VDD = 32.4V VSS = 0V 140 09769-108 160 Figure 8.
PAGE 11
Data Sheet ADG5236 100 500 I I (ON) + + IS (OFF) + – D, S 400 TA = +125°C 340 TA = +85°C 300 TA = +25°C 250 200 ID (OFF) – + 50 LEAKAGE CURRENT (pA) TA = –40°C 150 0 IS (OFF) – + –50 ID (OFF) + – –100 ID, IS (ON) – – 100 –150 50 VDD = 12V VSS = 0V 0 2 4 6 8 10 12 VS, VD (V) –200 09769-111 0 VDD = +20V VSS = –20V VBIAS = +15V/–15V 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 11. On Resistance vs.
PAGE 12
ADG5236 0 –20 Data Sheet 0 TA = 25°C VDD = +15V VSS = –15V –20 –40 ACPSRR (dB) IL (dB) –40 TA = 25°C VDD = +15V VSS = –15V –60 NO DECOUPLING CAPACITORS –60 –80 –80 –100 –100 1M 10M 100M 1G FREQUENCY (Hz) –120 1k 09769-117 100k 10k 100k 10M 1M FREQUENCY (Hz) Figure 17. Off Isolation vs. Frequency 09769-120 DECOUPLING CAPACITORS –120 10k Figure 20. ACPSRR vs.
PAGE 13
Data Sheet ADG5236 TA = 25°C VDD = +15V VSS = –15V 20 DRAIN OFF 10 5 SOURCE OFF 0 –15 –10 –5 0 5 10 VS (V) 15 09769-124 CAPACITANCE (pF) SOURCE/DRAIN ON 15 Figure 23. Capacitance vs. Source Voltage, Dual Supply Rev.
PAGE 14
ADG5236 Data Sheet TEST CIRCUITS ID (ON) IS (OFF) A A Dx NC = NO CONNECT VD SxA/SxB Dx ID (OFF) A VS VD Figure 24. On Leakage Figure 27. Off Leakage VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS SxA INx NC SxB 50Ω 50Ω VS V Dx VIN GND 09769-023 IDS VS OFF ISOLATION = 20 log Figure 25. On Resistance VDD 0.1µF VDD VDD SxA VSS 0.1µF VSS VDD RL 50Ω SxB VS VS VSS 0.1µF VOUT VOUT Figure 28. Off Isolation 0.
PAGE 15
Data Sheet ADG5236 VDD 0.1µF VSS VDD VIN 50% 50% VIN 50% 50% VSS SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF 90% VOUT 90% tON TRANSITION 09769-026 GND VIN tOFF TRANSITION Figure 30. Switching Times 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx VOUT SxA RL 300Ω INx VOUT CL 35pF 80% tD tD 09769-027 GND VIN Figure 31. Break-Before-Make Time Delay tD 3V ENABLE DRIVE (VIN) 50% 50% VDD VSS VDD VSS INx SxA VS SxB 0V tON (EN) tOFF (EN) OUTPUT 0.
PAGE 16
ADG5236 Data Sheet TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN is the digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay between applying the digital control input and the output switching on. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S.
PAGE 17
Data Sheet ADG5236 TRENCH ISOLATION NMOS PMOS P WELL N WELL In the ADG5236, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. Rev. B | Page 17 of 20 TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 34.
PAGE 18
ADG5236 Data Sheet APPLICATIONS INFORMATION The ADG52xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5236 high voltage switches allow singlesupply operation from 9 V to 40 V and dual supply operation from ±9 V to ±22 V. Rev.
PAGE 19
Data Sheet ADG5236 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.