Datasheet

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High Voltage Latch-Up Proof,

Triple/Quad SPDT Switches

Data Sheet

ADG5233/ADG5234

Rev. B Document Feedback

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FEATURES

Latch-up proof

4.5 pF off source capacitance

10 pF off drain capacitance

−0.6 pC charge injection

Low on resistance: 160 Ω typical

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

Human body model (HBM) ESD rating

4 kV I/O port to supplies

1 kV I/O port to I/O port

4 kV all other pins

APPLICATIONS

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. ADG5233 TSSOP and LFCSP_WQ

Figure 2. ADG5234 TSSOP and LFCSP_WQ

GENERAL DESCRIPTION

The ADG5233 and ADG5234 are monolithic industrial CMOS

analog switches comprising three independently selectable

single-pole, double throw (SPDT) switches and four indepen-

dently selectable SPDT switches, respectively.

All channels exhibit break-before-make switching action that

prevents momentary shorting when switching channels. An

input on the ADG5233 (LFCSP and TSSOP packages) is used to

enable or disable the device. When disabled, all channels are

switched off.

The ultralow capacitance and charge injection of these switches

make them ideal solutions for data acquisition and sample-and-

hold applications, where low glitch and fast settling are required.

Fast switching speed coupled with high signal bandwidth make

these devices suitable for video signal switching.

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors

thereby preventing latch-up even under severe overvoltage

conditions.

2. Ultralow Capacitance and −0.6 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5233/ADG5234 can be operated from dual supplies

up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5233/ADG5234 can be operated from a single-rail

power supply up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

Logic Power Supply Required.

S1A

S1B

S3B

S3A

S2B

S2A

ADG5233

IN1 IN2 IN3 EN

LOGIC

SWITCHES SHOWN FOR

A 1 INPUT LOGIC.

09919-001

ADG5234

SWITCHES SHOWN FOR

A 1 INPUT LOGIC.

IN1

S1B

S2B

IN2

S4A

IN4

S4B

S3B

IN3

S3A

09919-002

Summary of content (24 pages)

PAGE 1
High Voltage Latch-Up Proof, Triple/Quad SPDT Switches ADG5233/ADG5234 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 4.5 pF off source capacitance 10 pF off drain capacitance −0.
PAGE 2
ADG5233/ADG5234 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx ..............................8 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................9 Functional Block Diagrams .............................................................
PAGE 3
Data Sheet ADG5233/ADG5234 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 160 200 3.5 8 38 50 ±0.02 ±0.1 ±0.02 ±0.1 ±0.08 ±0.
PAGE 4
ADG5233/ADG5234 Parameter POWER REQUIREMENTS IDD ISS Data Sheet 25°C −40°C to +85°C 45 55 0.001 70 1 ±9/±22 VDD/VSS 1 −40°C to +125°C Unit µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2.
PAGE 5
Data Sheet Parameter CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS ADG5233/ADG5234 25°C 4.5 10 15 −40°C to +85°C −40°C to +125°C 50 70 0.001 110 1 ±9/±22 VDD/VSS 1 Unit pF typ pF typ pF typ µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test.
PAGE 6
ADG5233/ADG5234 Parameter Off Isolation Data Sheet 25°C −75 −40°C to +85°C Unit dB typ Channel-to-Channel Crosstalk −80 dB typ −3 dB Bandwidth 172 MHz typ Insertion Loss −8.
PAGE 7
Data Sheet Parameter Break-Before-Make Time Delay, tD ADG5233/ADG5234 25°C 65 −40°C to +85°C −40°C to +125°C Charge Injection, QINJ −0.6 Unit ns typ ns min pC typ Off Isolation −75 dB typ Channel-to-Channel Crosstalk −80 dB typ −3 dB Bandwidth Insertion Loss 190 −5.9 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 4.5 10 15 pF typ pF typ pF typ 35 80 100 VDD 1 130 9/40 Guaranteed by design; not subject to production test. Rev.
PAGE 8
ADG5233/ADG5234 Data Sheet CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 5. ADG5233 Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 24 42 16 26.
PAGE 9
Data Sheet ADG5233/ADG5234 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins ADG5233 ADG5234 Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 20-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) 20-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.
PAGE 10
ADG5233/ADG5234 Data Sheet D1 1 D3 10 S3A IN2 8 9 IN3 S2B 3 TOP VIEW (Not to Scale) D2 4 11 VSS 10 S3B 9 D3 S2A 5 S2A 7 ADG5233 09919-003 11 12 EN S1B 2 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 3. ADG5233 TSSOP Pin Configuration 09919-004 VSS TOP VIEW S2B 5 (Not to Scale) 12 S3B 13 D2 6 14 GND EN ADG5233 S1B 4 13 IN1 14 IN3 7 IN1 D1 3 S3A 8 GND 15 16 S1A 16 IN2 6 VDD 1 S1A 2 15 VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4.
PAGE 11
ADG5233/ADG5234 IN4 19 S4A D1 3 18 D4 S1B 4 17 S4B ADG5234 D1 S1B VSS GND S2B VDD TOP VIEW GND 6 (Not to Scale) 15 NC S2B 7 14 S3B D2 8 13 D3 S2A 9 12 S3A IN2 10 11 IN3 NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 1 2 3 4 5 ADG5234 TOP VIEW 15 14 13 12 11 D4 S4B VDD S3B D3 D2 6 S2A 7 IN2 8 IN3 9 S3A 10 16 09919-005 VSS 5 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 5.
PAGE 12
ADG5233/ADG5234 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 160 TA = 25°C TA = 25°C 140 VDD = +18V VSS = –18V 120 ON RESISTANCE (Ω) 120 100 VDD = +20V VSS = –20V 80 VDD = +22V VSS = –22V 60 100 60 40 20 20 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 80 40 0 09919-006 ON RESISTANCE (Ω) VDD = 32.4V VSS = 0V 140 0 10 5 15 20 25 30 35 40 VS, VD (V) 09919-009 160 Figure 10.
PAGE 13
Data Sheet ADG5233/ADG5234 500 100 ID (OFF) + – TA = +125°C 340 TA = +85°C 50 300 TA = +25°C 250 200 TA = –40°C 150 100 0 IS (OFF) – + –50 ID, IS (ON) – – ID, IS (ON) + + –100 –150 50 VDD = 12V VSS = 0V 0 2 6 4 12 10 8 VS, VD (V) 0 50 25 75 100 125 TEMPERATURE (°C) Figure 13.
PAGE 14
ADG5233/ADG5234 0 –20 Data Sheet 14 TA = 25°C VDD = +15V VSS = –15V TA = 25°C SOURCE TO DRAIN 12 VDD = +20V VSS = –20V CHARGE INJECTION (pC) OFF ISOLATION (dB) 10 –40 –60 –80 VDD = +15V VSS = –15V 8 VDD = +36V VSS = 0V 6 4 VDD = +12V VSS = 0V 2 0 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) –4 –20 09919-018 –120 10k –10 0 10 20 30 40 VS (V) 09919-020 –2 Figure 21. Charge Injection vs. Source Voltage, Source to Drain Figure 19. Off Isolation vs.
PAGE 15
Data Sheet 0 –2 ADG5233/ADG5234 TA = 25°C VDD = +15V VSS = –15V 20 TA = 25°C VDD = +15V VSS = –15V CAPACITANCE (pF) ATTENUATION (dB) SOURCE/DRAIN ON –4 –6 –8 15 DRAIN OFF 10 SOURCE OFF 5 1M 10M 100M 1G FREQUENCY (Hz) 300 250 VDD = +12V, VSS = 0V VDD = +36V, VSS = 0V VDD = +15V, VSS = –15V VDD = +20V, VSS = –20V 100 50 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 09919-024 TIME (ns) 200 0 –40 –10 –5 0 5 10 15 VS (V) Figure 25. Capacitance vs.
PAGE 16
ADG5233/ADG5234 Data Sheet TEST CIRCUITS IS (OFF) Dx Sx ID (OFF) Dx A A VD NC = NO CONNECT VS VD 09919-031 Sx A 09919-027 Figure 29. Off Leakage Figure 26. On Leakage VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS NC SxA IN SxB 50Ω 50Ω VS Dx VIN V RL 50Ω GND Dx 09919-028 IDS VS OFF ISOLATION = 20 log Figure 27. On Resistance VDD VOUT VSS VDD VSS 0.1µF 0.1µF VSS VDD NETWORK ANALYZER VSS NC Dx SxB VS VDD 0.1µF SxA RL 50Ω VOUT VS Figure 30. Off Isolation 0.
PAGE 17
Data Sheet ADG5233/ADG5234 0.1µF VDD VSS VDD VS 0.1µF VIN 50% 50% VIN 50% 50% VSS SxB Dx SxA VOUT RL 300Ω INx CL 35pF 90% VOUT 90% tON TRANSITION tOFF TRANSITION tD tD 09919-100 GND VIN Figure 32. Switching Timing VDD VSS 0.1µF VDD VSS SxB VS VIN Dx SxA VOUT RL 300Ω INx CL 35pF VOUT 80% GND VIN 09919-035 0.1µF Figure 33. Break-Before-Make Delay, tD 3V ENABLE DRIVE (VIN) 50% 50% VDD VSS VDD VSS INx SxA VS SxB 0V tON (EN) tOFF (EN) OUTPUT 0.
PAGE 18
ADG5233/ADG5234 Data Sheet TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN represents digital input capacitance. ISS ISS represents the negative supply current. tON (EN) tON (EN) represents the delay time between the 50% and 90% points of the digital input and switch on condition. VD, VS VD and VS represent the analog voltage on Terminal Dx and Terminal Sx, respectively.
PAGE 19
Data Sheet ADG5233/ADG5234 TRENCH ISOLATION In the ADG5233/ADG5234, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P WELL N WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 36. Trench Isolation Rev.
PAGE 20
ADG5233/ADG5234 Data Sheet APPLICATIONS INFORMATION The ADG52xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5233/ADG5234 high voltage switches allow singlesupply operation from 9 V to 40 V and dual supply operation from ±9 V to ±22 V. Rev.
PAGE 21
Data Sheet ADG5233/ADG5234 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.
PAGE 22
ADG5233/ADG5234 Data Sheet 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.75 2.60 SQ 2.35 11 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5 10 0.25 MIN BOTTOM VIEW 0.05 MAX 0.
PAGE 23
Data Sheet ADG5233/ADG5234 NOTES Rev.