Datasheet

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High Voltage Latch-Up Proof,

Quad SPST Switches

ADG5212/ADG5213

Rev. 0

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FEATURES

Latch-up proof

3 pF off source capacitance

5 pF off drain capacitance

0.07 pC charge injection

Low leakage: 0.2 nA maximum at 85ºC

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

APPLICATIONS

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

IN4

ADG5212

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

IN2

IN3

IN1

IN4

ADG5213

09767-001

Figure 1.

GENERAL DESCRIPTION

The ADG5212/ADG5213 contain four independent single-

pole/single-throw (SPST) switches. The ADG5212 switches

turn on with Logic 1. The ADG5213 has two switches with

digital control logic similar to that of the ADG5212; however,

the logic is inverted on the other two switches. Each switch

conducts equally well in both directions when on, and each

switch has an input signal range that extends to the supplies.

In the off condition, signal levels up to the supplies are blocked.

The ADG5212 and ADG5213 do not have a V

pin. The digital

inputs are compatible with 3 V logic inputs over the full

operating supply range.

The ultralow capacitance and charge injection of these switches

make them ideal solutions for data acquisition and sample-and-

hold applications, where low glitch and fast settling are required.

Fast switching speed together with high signal bandwidth make

the parts suitable for video signal switching.

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors,

thereby preventing latch-up even under severe overvoltage

conditions.

2. Ultralow Capacitance and <1 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5212/ADG5213 can be operated from dual supplies of

up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5212/ADG5213 can be operated from a single rail

power supply of up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

Logic Power Supply Required.

Summary of content (20 pages)

PAGE 1
High Voltage Latch-Up Proof, Quad SPST Switches ADG5212/ADG5213 FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 3 pF off source capacitance 5 pF off drain capacitance 0.07 pC charge injection Low leakage: 0.
PAGE 2
ADG5212/ADG5213 TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx..............................7 Applications....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagrams............................................................. 1 ESD Caution......
PAGE 3
ADG5212/ADG5213 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.
PAGE 4
ADG5212/ADG5213 ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) 25°C −40°C to +85°C −40°C to +125°C Unit VDD to VSS V max Ω typ 140 160 1.5 200 230 Ω max Ω typ 8 33 45 9 10 55 60 Ω max Ω typ Ω max LEAKAGE CURRENTS Source Off Leakage, IS (Off ) 0.01 0.1 0.01 0.2 Drain Off Leakage, ID (Off ) 0.1 0.
PAGE 5
ADG5212/ADG5213 Parameter POWER REQUIREMENTS IDD ISS 25°C −40°C to +85°C 50 70 0.001 110 1 ±9/±22 VDD/VSS 1 −40°C to +125°C Unit μA typ μA max μA typ μA max V min/V max Test Conditions/Comments VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
PAGE 6
ADG5212/ADG5213 Parameter Insertion Loss 25°C −11 CS (Off) CD (Off) CD (On), CS (On) POWER REQUIREMENTS IDD 3.5 5.5 9 −40°C to +85°C Unit dB typ pF typ pF typ pF typ 40 65 9/40 VDD 1 −40°C to +125°C μA typ μA max V min/V max Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test.
PAGE 7
ADG5212/ADG5213 Parameter −3 dB Bandwidth 25°C 410 Insertion Loss −6.8 dB typ 3 5 8 pF typ pF typ pF typ CS (Off) CD (Off) CD (On), CS (On) POWER REQUIREMENTS IDD −40°C to +85°C 80 100 Unit MHz typ μA typ μA max V min/V max 130 9/40 VDD 1 −40°C to +125°C Test Conditions/Comments RL = 50 Ω, CL = 5 pF, see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.
PAGE 8
ADG5212/ADG5213 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pin Continuous Current, Sx or Dx2 Temperature Operating Range Storage Range Junction Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free 1 2 Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.
PAGE 9
ADG5212/ADG5213 S1 1 VSS 2 TOP VIEW 12 NC (Not to Scale) S4 6 11 S3 GND 5 D3 IN4 8 9 IN3 NC = NO CONNECT TOP VIEW (Not to Scale) D4 5 10 S4 4 09767-002 D4 7 GND 3 ADG5212/ ADG5213 12 S2 11 VDD 10 NC 9 S3 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. 09767-003 VDD ADG5212/ ADG5213 14 IN2 S2 13 VSS 4 13 D2 14 D3 8 D2 S1 3 15 IN1 IN2 15 IN3 7 16 D1 2 IN4 6 IN1 1 16 D1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3.
PAGE 10
ADG5212/ADG5213 TYPICAL PERFORMANCE CHARACTERISTICS 160 TA = 25°C 140 VDD = +18V VSS = –18V ON RESISTANCE (Ω) 100 VDD = +20V VSS = –20V 80 VDD = +22V VSS = –22V 60 100 60 40 20 20 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) 0 0 TA = 25°C 5 10 15 20 25 30 35 40 VS, VD (V) Figure 4. RON as a Function of VS, VD (Dual Supply) 250 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 80 40 0 –25 VDD = 32.
PAGE 11
ADG5212/ADG5213 100 400 TA = +125°C 340 TA = +85°C 300 TA = +25°C 250 200 TA = –40°C 150 100 VDD = 12V VSS = 0V 0 IS (OFF) – + –50 ID (OFF) + – –100 ID, IS (ON) – – 2 4 6 8 10 12 VS, VD (V) –200 0 40 TA = +85°C TA = +25°C 100 TA = –40°C 50 125 ID, IS (ON) + + ID (OFF) – + 0 10 15 20 25 30 35 IS (OFF) – + –40 –60 ID (OFF) + – –80 –100 VS, VD (V) 0 25 75 100 50 IS (OFF) + – IS (OFF) + – ID, IS (ON) + + ID (OFF) – + 0 LEAKAGE CURRENT (pA) 0 –20 IS (OFF) – + –40
PAGE 12
ADG5212/ADG5213 0 0 –20 TA = 25°C VDD = +15V VSS = –15V –40 –40 ACPSRR (dB) OFF ISOLATION (dB) TA = 25°C VDD = +15V –20 VSS = –15V –60 –80 NO DECOUPLING CAPACITORS –60 –80 –100 –100 –120 1M 10M 100M 1G FREQUENCY (Hz) 09767-120 100k –120 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply 09767-123 DECOUPLING CAPACITORS –140 10k Figure 19. ACPSRR vs.
PAGE 13
ADG5212/ADG5213 0 –20 TA = 25°C VDD = +15V VSS = –15V TON (+12V) TON (+36V) TOFF (+36V) TOFF (±20V) TOFF (±15V) –60 –80 TON (±15V) TOFF (+12V) TON (±20V) –100 –120 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 09767-126 TIME (ns) –40 Figure 22. tON, tOFF Times vs. Temperature Rev.
PAGE 14
ADG5212/ADG5213 TEST CIRCUITS S D ID (OFF) A S VD A VS 09767-015 VS ID (ON) D VD Figure 26. On Leakage Figure 23. Off Leakage VDD VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VDD VSS S1 RL 50Ω Dx IDS VS GND V1 D RON = V1/IDS CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 24. On Resistance VDD Figure 27. Channel-to-Channel Crosstalk VDD VSS 0.1µF VDD NETWORK ANALYZER VSS Sx INx VSS 0.1µF 0.
PAGE 15
ADG5212/ADG5213 VDD VSS VSS D1 S2 D2 CL 35pF RL 300Ω IN1, IN2 RL 300Ω VOUT2 CL 35pF VOUT1 VOUT2 ADG5213 50% 90% 90% 0V 90% 90% 0V GND tD tD Figure 29. Break-Before-Make Time Delay, tD VDD VSS 0.1µF 0.1µF VIN Sx VS ADG5212 50% 50% VSS VOUT Dx CL 35pF RL 300Ω INx 90% VOUT 90% GND tOFF tON 09767-018 VDD Figure 30.
PAGE 16
ADG5212/ADG5213 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN is the digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay between applying the digital control input and the output switching on (see Figure 30). VD, VS VD and VS represent the analog voltage on Terminal Dx and Terminal Sx, respectively. RON RON represents the ohmic resistance between Terminal Dx and Terminal Sx.
PAGE 17
ADG5212/ADG5213 TRENCH ISOLATION In the ADG5212 and ADG5213, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P WELL N WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 32. Trench Isolation Rev.
PAGE 18
ADG5212/ADG5213 APPLICATIONS INFORMATION The ADG52xx family of switches and multiplexers provides a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5212/ADG5213 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. Rev.
PAGE 19
ADG5212/ADG5213 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.