Datasheet

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High Voltage, Latch-Up Proof,

4-/8-Channel Multiplexers

Data Sheet

ADG5208/ADG5209

Rev. A

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FEATURES

Latch-up proof

5.5 pF off source capacitance

52 pF off drain capacitance

0.4 pC charge injection

Low on resistance: 160 Ω typical

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

Human body model (HBM) ESD rating

4 kV I/O port to supplies

1 kV I/O port to I/O port

4 kV all other pins

APPLICATIONS

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAMS

ADG5208

1-OF-8

DECODER

A0 A1 A2 EN

ADG5209

S1A

S4A

S1B

S4B

1-OF-4

DECODER

A0 A1

09917-001

Figure 1.

GENERAL DESCRIPTION

The ADG5208/ADG5209 are monolithic CMOS analog multi-

plexers comprising eight single channels and four differential

channels, respectively. The ADG5208 switches one of eight

inputs to a common output, as determined by the 3-bit binary

address lines, A0, A1, and A2. The ADG5209 switches one of

four differential inputs to a common differential output, as

determined by the 2-bit binary address lines, A0 and A1.

An EN input on both devices enables or disables the device.

When EN is disabled, all channels switch off. The ultralow

capacitance and charge injection of these switches make them

ideal solutions for data acquisition and sample-and-hold appli-

cations, where low glitch and fast settling are required. Fast

switching speed coupled with high signal bandwidth make

these devices suitable for video signal switching.

Each switch conducts equally well in both directions when on,

and each switch has an input signal range that extends to the

power supplies. In the off condition, signal levels up to the

supplies are blocked.

The ADG5208/ADG5209 do not have V

pins; instead, the logic

power supply is generated internally by an on-chip voltage

generator.

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors

to prevent latch-up even under severe overvoltage conditions.

2. 0.4 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5208/ADG5209 can be operated from dual supplies

of up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5208/ADG5209 can be operated from a single rail

power supply of up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

Logic Power Supply Required.

Summary of content (24 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 5.5 pF off source capacitance 52 pF off drain capacitance 0.
PAGE 2
ADG5208/ADG5209 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................9 Applications ....................................................................................... 1 ESD Caution...................................................................................9 Functional Block Diagrams ...........................................
PAGE 3
Data Sheet ADG5208/ADG5209 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 160 200 3.5 8 40 50 ±0.005 ±0.1 ±0.005 ±0.1 ±0.01 ±0.
PAGE 4
ADG5208/ADG5209 Parameter CD (On), CS (On) ADG5208 ADG5209 POWER REQUIREMENTS IDD ISS Data Sheet 25°C −40°C to +85°C 58 31 45 55 0.001 Unit Test Conditions/Comments pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = −16.
PAGE 5
Data Sheet ADG5208/ADG5209 Parameter −3 dB Bandwidth ADG5208 ADG5209 Insertion Loss 25°C 60 130 −5.6 MHz typ MHz typ dB typ CS (Off ) CD (Off ) ADG5208 ADG5209 CD (On), CS (On) ADG5208 ADG5209 POWER REQUIREMENTS IDD 5.5 pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 32 VS = 0 V, f = 1 MHz 51 26 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 57 31 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD ISS −40°C to +85°C 50 70 0.
PAGE 6
ADG5208/ADG5209 Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION Data Sheet 25°C −40°C to +85°C −40°C to +125°C 330 380 345 400 160 175 Test Conditions/Comments RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 33 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 35 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 35 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 34 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 36 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see F
PAGE 7
Data Sheet Parameter Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ADG5208/ADG5209 25°C ±0.005 −40°C to +85°C −40°C to +125°C Unit nA typ ±0.1 ±0.01 ±0.2 ±0.4 ±1.4 VS = VD = 1 V/30 V; see Figure 27 ±0.5 ±1.4 nA max nA typ nA max V min V max µA typ µA max pF typ VIN = VGND or VDD 2.0 0.8 0.002 ±0.
PAGE 8
ADG5208/ADG5209 Data Sheet CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx Table 5. ADG5208 Parameter CONTINUOUS CURRENT, Sx OR D VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 40 69 24 37 14.5 18 mA maximum mA maximum 42 75 26.5 40 14.
PAGE 9
Data Sheet ADG5208/ADG5209 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7.
PAGE 10
ADG5208/ADG5209 Data Sheet D 8 9 S8 11 VDD S2 3 TOP VIEW (Not to Scale) 10 S5 9 S3 4 S6 S7 8 10 S7 ADG5208 S8 7 S4 7 12 GND S1 2 S4 5 11 S6 09917-002 S3 6 13 A2 VSS 1 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. Figure 2.
PAGE 11
GND VSS 3 14 VDD ADG5209 VSS 1 12 VDD S1A 2 ADG5209 11 S1B S3A 6 11 S3B S2A 3 TOP VIEW (Not to Scale) 10 S2B S4A 7 10 S4B DA 8 9 DB 09917-004 TOP VIEW 13 S1B S2A 5 (Not to Scale) 12 S2B 9 DB 7 S3B S4B 8 DA 6 S3A 4 S4A 5 S1A 4 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. Figure 4.
PAGE 12
ADG5208/ADG5209 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 160 TA = 25°C TA = 25°C 140 VDD = +18V VSS = –18V 120 ON RESISTANCE (Ω) 120 100 VDD = +20V VSS = –20V 80 VDD = +22V VSS = –22V 60 100 60 40 20 20 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 80 40 0 09917-006 ON RESISTANCE (Ω) VDD = 32.4V VSS = 0V 140 0 5 10 15 20 25 30 35 40 VS, VD (V) 09917-009 160 Figure 9.
PAGE 13
Data Sheet ADG5208/ADG5209 100 500 IS (OFF) + – 400 TA = +125°C 350 TA = +85°C 50 LEAKAGE CURRENT (pA) 300 TA = +25°C 250 200 TA = –40°C 150 ID (OFF) + – ID (OFF) – + 0 IS (OFF) – + –50 –100 ID, IS (ON) + + ID, IS (ON) – – 100 –150 50 VDD = 12V VSS = 0V 0 2 4 6 8 10 12 VS, VD (V) –200 09917-012 0 VDD = +20V VSS = –20V VBIAS = +15V/–15V 0 25 50 75 100 125 TEMPERATURE (°C) 09917-015 ON RESISTANCE (Ω) 450 Figure 15. Leakage Currents vs.
PAGE 14
ADG5208/ADG5209 Data Sheet 0 0 –20 –40 –60 –80 NO DECOUPLING CAPACITORS –60 –80 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) –120 1k 09917-018 –140 10k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply Figure 18. Off Isolation vs.
PAGE 15
Data Sheet ADG5208/ADG5209 350 80 300 70 VDD = +12V VSS = 0V 200 150 VDD = +20V VSS = –20V VDD = +15V VSS = –15V SOURCE/DRAIN ON 60 VDD = +36V VSS = 0V CAPACITANCE (pF) TIME (ns) 250 TA = 25°C VDD = +15V VSS = –15V 100 50 DRAIN OFF 40 30 20 50 10 0 20 40 60 80 100 120 TEMPERATURE (°C) 09917-024 –20 0 –15 Figure 24. tTRANSITION Times vs.
PAGE 16
ADG5208/ADG5209 Data Sheet TEST CIRCUITS ID (ON) IS (OFF) A A D VD NC = NO CONNECT ID (OFF) Sx D A 09917-031 Sx VD VS 09917-027 NC Figure 30. Off Leakage Figure 27. On Leakage VSS VDD 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx IDS 50Ω VS D V1 RL 50Ω GND VS RON = V1/IDS OFF ISOLATION = 20 log Figure 28. On Resistance VDD VSS VDD 0.1µF VSS 0.1µF 0.1µF VOUT VOUT VS Figure 31. Off Isolation 0.
PAGE 17
Data Sheet ADG5208/ADG5209 3V tr < 20ns tf < 20ns ADDRESS DRIVE (VIN) 50% 50% VDD VSS VDD VSS A0 S1 0V VIN VS1 A1 50Ω S2 TO S7 A2 tTRANSITION tTRANSITION VS8 S8 90% ADG5208* 2.0V OUTPUT OUTPUT D EN GND 300Ω 35pF 09917-034 90% *SIMILAR CONNECTION FOR ADG5209. Figure 33. Address to Output Switching Times, tTRANSITION VDD VSS VDD VSS 3V ADDRESS DRIVE (VIN) A0 S1 VIN 0V VS A1 50Ω S2 TO S7 A2 S8 80% ADG5208* 80% OUTPUT 2.
PAGE 18
ADG5208/ADG5209 Data Sheet 3V VDD VSS VDD VSS A0 A1 VIN A2 ADG5208* ΔVOUT S D EN QINJ = CL × ΔVOUT VS GND VOUT CL 1nF VIN *SIMILAR CONNECTION FOR ADG5209. Figure 36. Charge Injection Rev.
PAGE 19
Data Sheet ADG5208/ADG5209 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN represents digital input capacitance. ISS ISS represents the negative supply current. tON (EN) tON (EN) represents the delay time between the 50% and 90% points of the digital input and switch on condition. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively.
PAGE 20
ADG5208/ADG5209 Data Sheet TRENCH ISOLATION In the ADG5208/ADG5209, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P WELL N WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 37. Trench Isolation Rev.
PAGE 21
Data Sheet ADG5208/ADG5209 APPLICATIONS INFORMATION The ADG52xx family of switches and multiplexers provides a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The ADG5208/ADG5209 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. Rev.
PAGE 22
ADG5208/ADG5209 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.
PAGE 23
Data Sheet ADG5208/ADG5209 NOTES Rev.