Datasheet

ADG5206/ADG5207 Data Sheet
Rev. A | Page 24 of 28
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is turned
off. The ADG5206/ADG5207 high voltage switches allow single-
supply operation from 9 V to 40 V and dual-supply operation
from ±9 V to ±22 V.
TRENCH ISOLATION
In the ADG5206/ADG5207, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latch-
up proof switch.
Figure 42. Trench Isolation
NMOS PMOS
P WELL N WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
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