Datasheet

ADG5204
Rev. 0 | Page 15 of 20
V
DD
V
SS
V
DD
V
SS
V
IN
S1
D
GND
C
L
35pF
R
L
300Ω
V
OUT
V
OUT
50% 50%
90%
90%
ADDRESS
DRIVE (V
IN
)
A0
A1
S4
S3
S2
V
S1
V
S4
EN
2.4V
0V
3V
t
TRANSITION
t
TRANSITION
0.1µF
0.1µF
09768-012
Figure 29. Address to Output Switching Times
V
DD
V
SS
V
DD
V
SS
C
L
35pF
R
L
300Ω
ADDRESS
DRIVE (V
IN
)
V
OUT
V
OUT
V
IN
S1
D
GND
300Ω
A0
A1
S4
S3
S2
V
S1
EN
2.4V
0.1µF
0.1µF
t
D
80%
80%
0V
3V
09768-013
Figure 30. Break-Before-Make Time Delay, t
D
ENABLE
DRIVE (V
IN
)
S1
D
GND
C
L
35pF
R
L
300Ω
A0
A1
S4
S3
S2
EN
0.1µF
0.1µF
V
IN
300Ω
t
OFF
(EN)
t
ON
(EN)
50% 50%
0.9V
OUT
0.1V
OUT
OUTPUT
0V
3V
V
OUT
0V
V
DD
V
SS
V
DD
V
SS
V
S
V
OUT
09768-014
Figure 31. Enable-to-Output Switching Delay
Sx D
V
S
GND
R
S
SW OFF
SW OFF
SW ON
SW OFF
SW OFF
A2A1
EN
V
DD
V
SS
V
DD
DECODER
V
SS
V
OUT
V
OUT
V
IN
V
IN
∆V
OUT
C
L
1nF
Q
INJ
= C
L
× ∆V
OUT
09768-015
Figure 32. Charge Injection