Datasheet

ADG333A
Rev. A | Page 10 of 12
TEST CIRCUITS
V
D
I
DS
SD
R
ON
= V
1
/I
DS
V
1
01212-014
Figure 14. On Resistance
V
D
SD
I
S
(OFF)
V
S
01212-015
A
Figure 15. Off Leakage
V
D
SD
NC
NC = NO CONNECT
01212-016
I
D
(ON)
A
Figure 16. On Leakage
D
GND
IN
SA
SB
–10V
+10V
V
DD
V
DD
V
SS
V
SS
V
S
V
OUT
R
L
300Ω
C
L
35pF
0.1µF
0.1µF
50% 50%
50% 50%
t
ON
t
OFF
V
IN
V
S
+3V
0V
+10V
0V
–10V
01212-017
Figure 17. Switching Times
D
GND
IN
SA
SB
V
DD
V
DD
V
SS
V
SS
V
S
V
OUT
R
L
300Ω
C
L
35pF
0.1µF
0.1µF
01212-018
3V
0V
V
IN
V
OUT
V
S
50% 50%
t
OPEN
Figure 18. Break-Before-Make Delay, t
OPEN
V
DD
V
DD
V
SS
V
SS
V
OUT
IN
C
L
10nF
GND
V
IN
V
OUT
Q
INJ
= C
L
× ∆V
OUT
∆V
OUT
3V
0V
0V
DSA
V
D
R
D
01212-019
Figure 19. Charge Injection
V
SS
V
OUT
GND
SD
V
IN
V
S
01212-020
V
DD
V
DD
V
SS
0.1µF
0.1µF
R
L
75Ω
V
SS
GND
SD
V
IN1
V
S
01212-021
V
DD
V
DD
V
SS
0.1µF
0.1µF
V
OUT
NC
CHANNEL-TO-CHANNEL
CROSSTALK
20
× LOG |V
S
/V
OUT
|
V
IN2
75Ω
R
L
75Ω
SD
Figure 20. Off Isolation Figure 21. Channel-to-Channel Crosstalk