Datasheet
Data Sheet ADG3304
Rev. E | Page 19 of 21
APPLICATIONS INFORMATION
The ADG3304 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals are connected to the
Y pins. The ADG3304 can provide level translation in both
directions from A→Y or Y→A on all four channels, eliminating
the need for a level translator IC for each direction. The internal
architecture allows the ADG3304 to perform bidirectional level
translation without an additional signal to set the direction in
which the translation is made. It also allows simultaneous data
flow in both directions on the same part, for example, when two
channels translate in A→Y direction while the other two translate
in Y→A direction. This simplifies the design by eliminating the
timing requirements for the direction signal and reducing the
number of ICs used for level translation.
Figure 40 shows an application where two microprocessors
operating at 1.8 V and 3.3 V, respectively, can transfer data
simultaneously using two full-duplex serial links, TX1/RX1
and TX2/RX2.
V
CCY
Y1
Y2
Y3
Y4
EN
GND
A4
A3
A2
A1
V
CCA
ADG3304
MICROPROCESSOR/
MICROCONTROLLER/
DSP
1.8V
3.3V
MICROPROCESSOR/
MICROCONTROLLER/
DSP
100nF
100nF
TX1
RX2
TX2
RX1
RX1
TX2
RX2
TX1
GND
04860-056
GND
Figure 40. 1.8 V to 3.3 V Level Translation Circuit on
Two Full-Duplex Serial Links
When the application requires level translation between a micro-
processor and multiple peripheral devices, the ADG3304 I/O
pins can be three-stated by setting EN = 0. This feature allows
the ADG3304 to share the data buses with other devices without
causing contention issues. Figure 41 shows an application where
a 1.8 V microprocessor is connected to a 3.3 V peripheral
device using the three-state feature.
V
CCY
Y1
Y2
Y3
Y4
EN
GND
A4
A3
A2
A1
V
CCA
A
DG
3
304
MICROPROCESSOR/
MICROCONTROLLER/
DSP
CS
1.8V
3.3V
PERIPHERAL
DEVICE 1
100nF
100nF
I/O
L1
I/O
L4
I/O
L3
I/O
L2
I/O
H1
I/O
H4
I/O
H3
I/O
H2
GND
04860-055
100nF
100nF
GND
V
CCY
Y1
Y2
Y3
Y4
EN
GND
A4
A3
A2
A1
V
CCA
ADG3304
3.3V
PERIPHERAL
DEVICE 2
I/O
H1
I/O
H4
I/O
H3
I/O
H2
GND
Figure 41. 1.8 V to 3.3 V Level Translation Circuit
Using the Three-State Feature
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V
CC
pin (V
CCA
and
V
CCY
) should be bypassed using low effective series resistance
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V
CCA
pin and the V
CCY
pin. The parasitic
inductance of the high speed signal track may cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.
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