Datasheet

Data Sheet ADG3304
Rev. E | Page 17 of 21
THEORY OF OPERATION
The ADG3304 level translator allows the level shifting necessary
for data transfer in a system where multiple supply voltages are
used. The device requires two supplies, V
CCA
and V
CCY
(V
CCA
≤
V
CCY
). These supplies set the logic levels on each side of the
device. When driving the A pins, the device translates the V
CCA
-
compatible logic levels to V
CCY
-compatible logic levels available
at the Y pins. Similarly, because the device is capable of
bidirectional translation, when driving the Y pins, the V
CCY
-
compatible logic levels are translated to V
CCA
-compatible logic
levels available at the A pins. When EN = 0, Pin A1 to Pin A4
and Pin Y1 to Pin Y4 are three-stated. When EN is driven high,
the ADG3304 goes into normal operation mode and performs
level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3304 consists of four bidirectional channels. Each
channel can translate logic levels in either the A→Y or the Y→A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 39 shows a
simplified block diagram of a bidirectional channel.
ONE-SHOT GENERATOR
6kΩ
6kΩ
Y
V
CCA
V
CCY
T2T1
T3T4
A
04860-053
P
N
U1
U2
U4
U3
Figure 39. Simplified Block Diagram of an ADG3304 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using Inverter U3
and Inverter U4. The one-shot generator detects a rising or
falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transistors
(T1 to T2) for a rising edge, or the NMOS transistors (T3 to T4)
for a falling edge. This charges/discharges the capacitive load
faster, which results in faster rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding V
CC
rail (V
CCA
or V
CCY
) or to GND.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3304, the circuit that
drives the input of the ADG3304 channels should have an
output impedance of less than or equal to 150 Ω and a
minimum peak current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3304 level translator is designed to drive CMOS-
compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3304 outputs
and the load.
ENABLE OPERATION
The ADG3304 provides three-state operation at the A and Y
I/O pins by using the enable pin (EN), as shown in Table 5.
Table 5. Truth Table
EN Y I/O Pins A I/O Pins
0 Hi-Z
1
Hi-Z
1
1 Normal operation
2
Normal operation
2
1
High impedance state.
2
In normal operation, the ADG3304 performs level translation.
While EN = 0, the ADG3304 enters into three-state mode. In this
mode, the current consumption from both the V
CCA
and V
CCY
supplies is reduced, allowing the user to save power, which is
critical, especially on battery-operated systems. The EN input pin
can be driven with either V
CCA
-compatible or V
CCY
-compatible
logic levels.
POWER SUPPLIES
For proper operation of the ADG3304, the voltage applied to
the V
CCA
must be less than or equal to the voltage applied to V
CCY
.
To meet this condition, the recommended power-up sequence
is V
CCY
first and then V
CCA
. The ADG3304 operates properly
only after both supply voltages reach their nominal values. It is
not recommended to use the part in a system where, during
power-up, V
CCA
can be greater than V
CCY
due to a significant
increase in the current taken from the V
CCA
supply. For
optimum performance, the V
CCA
pin and V
CCY
pin should be
decoupled to GND as close as possible to the device.
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