Datasheet

ADG3304 Data Sheet
Rev. E | Page 16 of 21
TERMINOLOGY
V
IHA
Logic input high voltage at Pin A1 to Pin A4.
V
ILA
Logic input low voltage at Pin A1 to Pin A4.
V
OHA
Logic output high voltage at Pin A1 to Pin A4.
V
OLA
Logic output low voltage at Pin A1 to Pin A4.
C
A
Capacitance measured at Pin A1 to Pin A4 (EN = 0).
I
LA, Hi-Z
Leakage current at Pin A1 to Pin A4 when EN = 0 (high
impedance state at Pin A1 to Pin A4).
V
IHY
Logic input high voltage at Pin Y1 to Pin Y4.
V
ILY
Logic input low voltage at Pin Y1 to Pin Y4.
V
OHY
Logic output high voltage at Pin Y1 to Pin Y4.
V
OLY
Logic output low voltage at Pin Y1 to Pin Y4.
C
Y
Capacitance measured at Pin Y1 to Pin Y4 (EN = 0).
I
LY, Hi-Z
Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high
impedance state at Pin Y1 to Pin Y4).
V
IHEN
Logic input high voltage at the EN pin.
V
ILEN
Logic input low voltage at the EN pin.
C
EN
Capacitance measured at EN pin.
I
LEN
Enable (EN) pin leakage current.
t
EN
Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to
Pin Y4.
t
P, A →Y
Propagation delay when translating logic levels in the A→Y
direction.
t
R, A→Y
Rise time when translating logic levels in the A→Y direction.
T
F, A →Y
Fall time when translating logic levels in the A→Y direction.
D
MAX, A→Y
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
Table 1.
T
S K E W, A →Y
Difference between propagation delays on any two channels
when translating logic levels in the A→Y direction.
t
PPSKEW, A→Y
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A→Y direction.
t
P, Y →A
Propagation delay when translating logic levels in the Y→A
direction.
t
R, Y→A
Rise time when translating logic levels in the Y→A direction.
t
F, Y →A
Fall time when translating logic levels in the Y→A direction.
D
MAX, Y→A
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
Table 1.
t
S K E W, Y → A
Difference between propagation delays on any two channels
when translating logic levels in the Y→A direction.
t
PPSKEW, Y→A
Difference in propagation delay between any one channel and
the same channel on a different part (under the same driving/
loading conditions) when translating in the Y→A direction.
V
CCA
V
CCA
supply voltage.
V
CCY
V
CCY
supply voltage.
I
CCA
V
CCA
supply current.
I
CCY
V
CCY
supply current.
I
Hi-Z, A
V
CCA
supply current during three-state mode (EN = 0).
I
Hi-Z, Y
V
CCY
supply current during three-state mode (EN = 0).
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