Datasheet

ADG3248
Rev. A | Page 11 of 12
MULTIPLEXING
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common problems
faced by designers of these systems include
• Large delays caused by capacitive loading of the bus
• Noise due to simultaneous switching of the address and
data bus signals
Figure 25 shows an array of memory banks in which each
address and data signal is loaded by the sum of the individual
loads. If a bus switch is used as shown in
Figure 26, the output
load on the memory address and data bits is halved. The speed
at which data from the selected bank can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
MEMORY
A
DDRESS DATA
MEMORY
BANK A
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
04404-025
Figure 25. All Memory Banks Are Permanently Connected to the Bus
MEMORY
A
DDRESS
DATA
MEMORY
BANK A
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
04404-026
ADG3248 ADG3248
Figure 26. ADG3248 Used to Reduce Both Access Time and Noise