Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LFCSP-32-VQ

CMOS 8 × 8 Unbuffered Analog

Switch Array with Dual/Single Supplies

ADG2188

Rev. 0

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FEATURES

C-compatible interface

3.4 MHz high speed I

C option

32-lead LFCSP_VQ (5 mm × 5 mm)

Double-buffered input logic

Simultaneous update of multiple switches

Up to 300 MHz bandwidth

Fully specified at dual ±5 V/single +12 V operation

On resistance 35 Ω maximum

Low quiescent current < 20 μA

APPLICATIONS

AV switching in TV

Automotive infotainment

AV receivers

CCTV

Ultrasound applications

KVM switching

Telecom applications

Test equipment/instrumentation

PBX systems

GENERAL DESCRIPTION

The ADG2188 is an analog cross point switch with an

array size of 8 × 8. The switch array is arranged so that

there are eight columns by eight rows, for a total of 64

switch channels. The array is bidirectional, and the rows and

columns can be configured as either inputs or outputs. Each

of the 64 switches can be addressed and configured through

the I

C-compatible interface. Standard, full speed, and high

speed (3.4 MHz) I

C interfaces are supported. Any

simultaneous switch combination is allowed. An additional

feature of the ADG2188 is that switches can be updated

simultaneously, using the LDSW command. In addition,

RESET

option allows all of the switch channels to be

reset/off. At power on, all switches are in the off condition.

The device is packaged in a 32-lead, 5 mm × 5 mm

LFCSP_VQ.

FUNCTIONAL BLOCK DIAGRAM

ADG2188

SCL

X0 TO X7 (I/O)

8 × 8 SWITCH ARRAY

LDSW

INPUT

AND

7 TO 64

DECODER

LATCHES

LDSW

GNDA0A1A2

Y0 TO Y7 (I/O)

5897-001

Figure 1.

Summary of content (28 pages)

PAGE 1
I2C® CMOS 8 × 8 Unbuffered Analog Switch Array with Dual/Single Supplies ADG2188 FEATURES GENERAL DESCRIPTION I2C-compatible interface 3.4 MHz high speed I2C option 32-lead LFCSP_VQ (5 mm × 5 mm) Double-buffered input logic Simultaneous update of multiple switches Up to 300 MHz bandwidth Fully specified at dual ±5 V/single +12 V operation On resistance 35 Ω maximum Low quiescent current < 20 μA The ADG2188 is an analog cross point switch with an array size of 8 × 8.
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ADG2188 TABLE OF CONTENTS Features .............................................................................................. 1 Load Switch (LDSW)................................................................. 18 Applications....................................................................................... 1 Readback ..................................................................................... 18 General Description .....................................................................
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ADG2188 SPECIFICATIONS VDD = 12 V ± 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Channel Off Leakage, IOFF Channel On Leakage, ION DYNAMIC CHARACTERISTICS 2 COFF CON tON tOFF THD + N B Version −40°C to +25°C +85°C VDD − 2 V 30 35 32 37 45 50 4.5 8 2.3 3.5 14.
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ADG2188 Parameter LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH B Version −40°C to +85°C +25°C 0.7 VL VL + 0.3 −0.3 0.3 VL Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL Floating State Leakage Current POWER REQUIREMENTS IDD Y Version −40°C to +125°C +25°C 0.005 0.7 VL VL + 0.3 −0.3 0.3 VL 0.005 ±1 0.05 VL 7 ±1 0.05 VL 7 0.4 0.6 ±1 0.05 0.4 0.6 ±1 0.05 1 ISS 0.05 1 0.05 1 IL Interface Inactive 1 0.
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ADG2188 VDD = +5 V ± 10% , VSS = −5 V ± 10% , VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) B Version −40°C to +25°C +85°C Y Version −40°C to +25°C +125°C 34 40 50 55 66 75 4.5 8 17 20 34 34 40 50 55 66 75 4.
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ADG2188 Parameter Input Hysteresis Input Capacitance, CIN LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL Floating State Leakage Current POWER REQUIREMENTS IDD B Version −40°C to +25°C +85°C 0.05 VL 7 Y Version −40°C to +25°C +125°C 0.05 VL 7 0.4 0.6 ±1 0.05 0.4 0.6 ±1 0.005 1 ISS 0.05 1 0.005 1 1 Unit V min pF typ Conditions V max V max μA max ISINK = 3 mA ISINK = 6 mA μA typ μA max μA typ μA max Digital inputs = 0 V or VL IL Digital inputs = 0 V or VL Interface Inactive 0.
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ADG2188 I2C TIMING SPECIFICATIONS VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2). Table 3.
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ADG2188 Parameter 1 t11 t11A t12 tSP ADG2188 Limit at TMIN, TMAX Min Max Unit 1000 ns 20 + 0.1 CB 300 ns Conditions Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Fast mode High speed mode2 10 20 40 80 1000 300 ns ns ns ns 20 + 0.
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ADG2188 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
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ADG2188 27 26 25 24 VDD 23 NC 22 NC 21 NC 20 NC 19 NC 7 18 X7 8 17 X6 X3 6 X4 X5 8×8 TOP VIEW (Not to Scale) 9 10 11 12 13 14 15 16 Y7 5 Y6 X2 ADG2188 Y5 4 Y3 X1 Y4 3 Y2 X0 PIN 1 INDICATOR Y0 2 Y1 NC NC = NO CONNECT 05897-003 VL 28 SCL 29 SDA 30 A1 31 A0 RESET 32 VSS 1 A2 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Exposed Paddle Soldered to VSS Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1 Pin No.
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ADG2188 TYPICAL PERFORMANCE CHARACTERISTICS 90 200 TA = 25°C IDS = 10mA TA = 25°C 180 IDS = 10mA 80 160 VDD = 7.2V VSS = –5V VDD = +5V 120 RON (Ω) RON (Ω) 70 VSS = 0V VDD = +8V 140 100 80 VDD = 8V 60 50 60 VDD = 8.8V VSS = 0V VDD = +12V 40 40 30 1 2 3 4 5 6 7 8 9 10 11 12 SOURCE VOLTAGE (V) 05897-007 0 –5 –4 –3 –2 –1 0 0 0.5 2.0 2.5 3.0 3.5 4.0 5.0 4.5 Figure 7. RON vs.
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ADG2188 80 18 VDD = 8V VSS = 0V IDS = 10mA TA = +125°C 60 TA = +85°C 50 RON (Ω) Y CHANNELS, VBIAS = 7V 14 LEAKAGE CURRENTS (nA) 70 VDD = 12V VSS = 0V 16 40 TA = +25°C 30 TA = –40°C 20 X CHANNELS, VBIAS = 7V 12 10 8 Y CHANNELS, VBIAS = 1V 6 4 2 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
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ADG2188 0 240 –1 220 tOFF INSERTION LOSS (dB) VDD = +5V, VSS = –5V 180 tON 160 VDD = 12V, VSS = 0V 140 –2 –3 –4 –5 –6 –7 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) –8 10 05897-029 100 –40 –10 –20 INSERTION LOSS (dB) –4 –5 –6 10G VDD = +5V TO +12V VSS = –5V TO 0V TA = 25°C –40 –50 –60 –70 –80 1k 100k 10M 1G 10G –110 10 1k 100k 10M 1G 05897-023 –100 1G FREQUENCY (Hz) Figure 17. Individual Inputs to Individual Outputs Bandwidth, Dual ±5 V Supply Figure 20.
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ADG2188 0.35 0 VDD = +5V VSS = –5V 0.30 VDD = 5V/12V VSS = –5V/0V TA = 25°C 0.2V p-p RIPPLE –20 VL = 5V SWITCH ON, WITHOUT DECOUPLING 0.25 ACPSRR (dB) 0.15 –60 –80 0.10 –100 0.5 1.0 1.5 2.0 2.5 –120 100 05897-016 0 3.0 FREQUENCY (MHz) 1.6 VL = 5V IL (mA) 1.2 1.0 0.8 0.6 0.4 0 1 2 3 VLOGIC (V) 4 5 6 05897-019 VL = 3V 0.2 10k 100k 1M 10M Figure 24. ACPSRR 1.8 1.4 1k FREQUENCY (Hz) Figure 22. Digital Current (IL) vs. Frequency 0 WITH DECOUPLING VL = 3V 0.
PAGE 15
ADG2188 TEST CIRCUITS The test circuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix. IDS V1 RON = V1/IDS X Y IOFF A VX VY Figure 25. On Resistance X NC VDD VSS VDD VSS X A VY Figure 27. On Leakage Figure 26. Off Leakage 0.1µF ION Y 0.1µF 50% 9TH DATA BIT VOUT Y RL 300Ω VX CL 35pF 90% VOUT tOFF AND tON 05897-034 GND Figure 28. Switching Times, tON, tOFF VDD VSS VDD VSS RX X 0.
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ADG2188 VDD VSS 0.1µF NETWORK ANALYZER 0.1µF VDD VOUT RL 50Ω VSS Y1 X1 X2 Y2 R 50Ω 50Ω DATA BIT CHANNEL-TO-CHANNEL CROSSTALK = 20 log GND VOUT VS 05897-038 VX R 50Ω Figure 32. Channel-to-Channel Crosstalk Rev.
PAGE 17
ADG2188 TERMINOLOGY On Resistance (RON) The series on-channel resistance measured between the X input/output and the Y input/output. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. On Resistance Match (ΔRON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB.
PAGE 18
ADG2188 THEORY OF OPERATION The ADG2188 is an analog cross point switch with an array size of 8 × 8. The eight rows are referred to as the X input/output lines, and the eight columns are referred to as the Y input/output lines. The device is fully flexible in that it connects any X line or number of X lines with any Y line when turned on. Similarly, it connects any X line with any number of Y lines when turned on. LOAD SWITCH (LDSW) Control of the ADG2188 is carried out via an I2C interface.
PAGE 19
ADG2188 SERIAL INTERFACE The ADG2188 is controlled via an I2C-compatible serial bus. The parts are connected to this bus as a slave device (no clock is generated by the switch). 2. The peripheral whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse, known as the acknowledge bit. At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register.
PAGE 20
ADG2188 WRITING TO THE ADG2188 INPUT SHIFT REGISTER The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
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ADG2188 DB15 DATA X X X X 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 DB14 AX3 1 1 1 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB13 AX2 1 1 1 1 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 DB12 AX1 0 0 1 1 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 DB11 AX0 0 1 0 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB10 AY2 0 0 0 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 1 1 .. 1 1 1 .. 1 1 1 .. 1 1 1 ..
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ADG2188 WRITE OPERATION When writing to the ADG2188, the user must begin with an address byte and R/W bit, after which the switch acknowledges that it is prepared to receive data by pulling SDA low. This address byte is followed by the two 8-bit words. The write operations for the switch array are shown in Figure 34. Note that it is only the condition of the switch corresponding to the bits in the data bytes that changes state. All other switches retain their previous condition. 2.
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ADG2188 SCL A2 SDA START COND BY MASTER A1 A0 RB7 R/W ACK BY SWITCH ADDRESS BYTE RB6 RB5 RB4 RB3 RB2 RB1 RB0 DATA BYTE x x x ACK BY SWITCH x x x x x NO ACK BY SWITCH DATA BYTE STOP COND BY MASTER SCL START COND BY MASTER ADDRESS BYTE A1 A0 R/W ACK BY SWITCH Y7 DUMMY READBACK BYTE Figure 35. Read Operation Rev.
PAGE 24
ADG2188 EVALUATION BOARD The ADG2188 evaluation board allows designers to evaluate the high performance 8 × 8 switch array of the ADG2188 with a minimum of effort. The evaluation kit includes a populated, tested ADG2188 printed circuit board. The evaluation board interfaces to the USB port of a PC, or it can be used as a standalone evaluation board. Software is available with the evaluation board that allows the user to easily program the ADG2188 through the USB port.
PAGE 25
ADG2188 05897-041 SCHEMATICS Figure 36. EVAL-ADG2188EB Schematic, USB Controller Section Rev.
PAGE 26
05897-042 ADG2188 Figure 37. EVAL-ADG2188EB Schematic, Chip Section Rev.
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ADG2188 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 25 24 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 38.
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ADG2188 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05897-0-4/06(0) Rev.