Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LFCSP-32-VQ

CMOS 8 × 12 Unbuffered Analog

Switch Array With Dual/Single Supplies

Data Sheet

ADG2128

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

C-compatible interface

3.4 MHz high speed I

C option

32-lead LFCSP_VQ (5 mm × 5 mm)

Double-buffered input logic

Simultaneous update of multiple switches

Up to 300 MHz bandwidth

Fully specified at dual ±5 V/single +12 V operation

On resistance 35 Ω maximum

Low quiescent current < 20 µA

Qualified for automotive applications

APPLICATIONS

AV switching in TV

Automotive infotainment

AV receivers

CCTV

Ultrasound applications

KVM switching

Telecom applications

Test equipment/instrumentation

PBX systems

GENERAL DESCRIPTION

The ADG2128 is an analog cross point switch with an

array size of 8 × 12. The switch array is arranged so that

there are eight columns by 12 rows, for a total of 96 switch

channels. The array is bidirectional, and the rows and columns

can be configured as either inputs or outputs. Each of the 96

switches can be addressed and configured through the I

C-

compatible interface. Standard, full speed, and high speed

(3.4 MHz) I

C interfaces are supported. Any simultaneous

switch combination is allowed. An additional feature of the

ADG2128 is that switches can be updated simultaneously,

using the LDSW command. In addition, a

RESET

option

allows all of the switch channels to be reset/off. At power-on,

all switches are in the off condition. The device is packaged

in a 32-lead, 5 mm × 5 mm LFCSP_VQ.

FUNCTIONAL BLOCK DIAGRAM

ADG2128

SCL

SDA

X0 TO X11 (I/O)

8 × 12 SWITCH ARRAY

LDSW

INPUT

AND

7 TO 96

DECODER

LATCHES

LDSW

GNDA0A1A2

Y0 TO Y7 (I/O)

05464-001

Figure 1.

Summary of content (28 pages)

PAGE 1
I2C® CMOS 8 × 12 Unbuffered Analog Switch Array With Dual/Single Supplies ADG2128 Data Sheet FEATURES GENERAL DESCRIPTION I2C-compatible interface 3.
PAGE 2
ADG2128 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Load Switch (LDSW) ................................................................. 18 Applications ....................................................................................... 1 Readback ..................................................................................... 18 General Description ......................................................
PAGE 3
Data Sheet ADG2128 SPECIFICATIONS VDD = 12 V ± 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Channel Off Leakage, IOFF Channel On Leakage, ION DYNAMIC CHARACTERISTICS 2 COFF CON tON tOFF THD + N B Version −40°C to +25°C +85°C VDD − 2 V 30 35 32 37 45 50 4.5 8 2.3 3.5 14.
PAGE 4
ADG2128 Parameter LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH Data Sheet B Version −40°C to +25°C +85°C 0.7 VL VL + 0.3 −0.3 0.3 VL Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL Floating State Leakage Current POWER REQUIREMENTS IDD Y Version −40°C to +25°C +125°C 0.005 0.7 VL VL + 0.3 −0.3 0.3 VL 0.005 ±1 0.05 VL 7 ±1 0.05 VL 7 0.4 0.6 ±1 0.05 0.4 0.6 ±1 0.05 1 ISS 0.05 1 0.
PAGE 5
Data Sheet ADG2128 VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 2.
PAGE 6
ADG2128 Parameter Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL Floating State Leakage Current POWER REQUIREMENTS IDD Data Sheet B Version −40°C to +25°C +125°C 0.005 ±1 0.05 VL 7 Y Version −40°C to +25°C +125°C 0.005 ±1 0.05 VL 7 0.4 0.6 ±1 0.05 0.4 0.6 ±1 0.005 1 ISS 0.05 1 0.
PAGE 7
Data Sheet ADG2128 I2C TIMING SPECIFICATIONS VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2). Table 3.
PAGE 8
ADG2128 Parameter 1 t11 t11A t12 tSP Data Sheet ADG2108 Limit at TMIN, TMAX Min Max 1000 20 + 0.1 CB 300 Conditions Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Fast mode High speed mode2 10 20 Unit ns ns 40 80 1000 300 ns ns ns ns 20 + 0.
PAGE 9
Data Sheet ADG2128 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
PAGE 10
ADG2128 Data Sheet VL 28 27 26 25 24 PIN 1 INDICATOR VDD 23 NC 22 X11 21 X10 20 X9 19 X8 7 18 X7 8 17 X6 X4 X5 9 10 11 12 13 14 15 16 Y7 6 Y6 5 X3 12 × 8 TOP VIEW (Not to Scale) Y5 X2 ADG2128 Y4 4 Y2 X1 Y3 3 Y0 2 X0 Y1 NC NOTES 1. THE EXPOSED PADDLE IS SOLDERED TO VSS. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 05464-003 SDA 29 A0 30 SCL A2 31 A1 GND 32 VSS 1 RESET PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3.
PAGE 11
Data Sheet ADG2128 TYPICAL PERFORMANCE CHARACTERISTICS 90 200 TA = 25°C IDS = 10mA TA = 25°C 180 IDS = 10mA 80 160 VDD = 7.2V VSS = –5V VDD = +5V 120 RON (Ω) RON (Ω) 70 VSS = 0V VDD = +8V 140 100 80 VDD = 8V 60 50 60 VDD = 8.8V VSS = 0V VDD = +12V 20 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 05464-025 40 05464-007 40 30 0 9 10 11 12 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 4. Signal Range 3.0 3.5 4.0 4.5 5.0 Figure 7. RON vs.
PAGE 12
ADG2128 Data Sheet 80 18 VDD = 8V VSS = 0V IDS = 10mA TA = +125°C 60 TA = +85°C 50 RON (Ω) Y CHANNELS, VBIAS = 7V 14 LEAKAGE CURRENTS (nA) 70 VDD = 12V VSS = 0V 16 40 TA = +25°C 30 TA = –40°C 20 X CHANNELS, VBIAS = 7V 12 10 8 Y CHANNELS, VBIAS = 1V 6 4 05464-013 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 05464-011 2 10 0 –2 0 4.0 20 40 Figure 10. RON vs.
PAGE 13
Data Sheet ADG2128 0 240 –1 TOFF VDD = 5V, VSS = 0V 180 TON 160 VDD = 12V, VSS = 0V 140 –2 –3 –4 –5 –6 100 –40 –7 05464-029 120 –20 0 20 40 60 80 100 –8 10 120 VDD = +5V VSS = –5V TA = 25°C 05464-022 TON/TOFF (ns) 200 INSERTION LOSS (dB) 220 1k Figure 16. TON/TOFF Times vs.
PAGE 14
ADG2128 0.35 Data Sheet 0 VDD = +5V VSS = –5V VDD = 5V/12V VSS = –5V/0V TA = 25°C –20 0.2V p-p RIPPLE 0.30 VL = 5V SWITCH ON, WITHOUT DECOUPLING 0.25 ACPSRR (dB) IL (mA) –40 0.20 0.15 SWITCH OFF, WITHOUT DECOUPLING –60 –80 0.10 WITH DECOUPLING VL = 3V 05464-016 0 0 0.5 1.0 1.5 2.0 2.5 –120 100 3.0 FREQUENCY (MHz) 1.6 1.4 VL = 5V IL (mA) 1.2 1.0 0.8 0.6 0.4 VL = 3V 05464-019 0.2 0 2 3 10k 100k 1M 10M Figure 24. ACPSRR 1.8 1 1k FREQUENCY (Hz) Figure 22.
PAGE 15
Data Sheet ADG2128 TEST CIRCUITS The test circuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix. IDS V1 Y A ION VY VX Figure 25. On Resistance X NC VDD VSS VDD VSS X A VY Figure 26. Off Leakage 0.1µF Y Figure 27. On Leakage 0.1µF 50% 9TH DATA BIT VOUT Y 90% RL 300Ω VX CL 35pF VOUT tOFF AND tON 05464-034 RON = V1/IDS IOFF X GND Figure 28. Switching Times, tON, tOFF RX VDD VSS VDD VSS X 0.
PAGE 16
ADG2128 Data Sheet VDD VSS 0.1µF NETWORK ANALYZER 0.1µF VDD VOUT RL 50Ω VSS Y1 X1 X2 Y2 R 50Ω 50Ω DATA BIT CHANNEL-TO-CHANNEL CROSSTALK = 20 log GND VOUT VS 05464-038 VX R 50Ω Figure 32. Channel-to-Channel Crosstalk Rev.
PAGE 17
Data Sheet ADG2128 TERMINOLOGY On Resistance (RON) The series on-channel resistance measured between the X input/output and the Y input/output. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. On Resistance Match (∆RON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB.
PAGE 18
ADG2128 Data Sheet THEORY OF OPERATION The ADG2128 is an analog cross point switch with an array size of 8 × 12. The 12 rows are referred to as the X input/output lines, while the eight columns are referred to as the Y input/output lines. The device is fully flexible in that it connects any X line or number of X lines with any Y line when turned on. Similarly, it connects any X line with any number of Y lines when turned on. LOAD SWITCH (LDSW) Control of the ADG2128 is carried out via an I2C interface.
PAGE 19
Data Sheet ADG2128 SERIAL INTERFACE The ADG2128 is controlled via an I2C-compatible serial bus. The parts are connected to this bus as a slave device (no clock is generated by the switch). 2. The peripheral whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse, known as the acknowledge bit. At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register.
PAGE 20
ADG2128 Data Sheet WRITING TO THE ADG2128 INPUT SHIFT REGISTER The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
PAGE 21
Data Sheet DB15 DATA 1 0 1 0 1 0 X X 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 DB14 AX3 1 1 1 1 1 1 1 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 ADG2128 DB13 AX2 0 0 1 1 1 1 1 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB12 AX1 1 1 0 0 0 0 1 1 0 0 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 DB11 AX0 1 1 0 0 1 1 0 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB10 AY2 0 0 0 0 0 0 0 0 0 0 .. 0 0 0 .. 0 0 0 ..
PAGE 22
ADG2128 Data Sheet WRITE OPERATION When writing to the ADG2128, the user must begin with an address byte and R/W bit, after which the switch acknowledges that it is prepared to receive data by pulling SDA low. This address byte is followed by the two 8-bit words. The write operations for the switch array are shown in Figure 34. Note that it is only the condition of the switch corresponding to the bits in the data bytes that changes state. All other switches retain their previous condition. 2.
PAGE 23
Data Sheet ADG2128 SCL A2 SDA START COND BY MASTER A1 A0 RB7 R/W ACK BY SWITCH ADDRESS BYTE RB6 RB5 RB4 RB3 RB2 RB1 DATA BYTE RB0 x x x ACK BY SWITCH x x x x x NO ACK BY SWITCH DATA BYTE STOP COND BY MASTER SCL START COND BY MASTER ADDRESS BYTE A1 A0 Y7 R/W ACK BY SWITCH DUMMY READBACK BYTE Figure 35. Read Operation Rev.
PAGE 24
ADG2128 Data Sheet EVALUATION BOARD The ADG2128 evaluation board allows designers to evaluate the high performance ADG2128 8 × 12 switch array with minimum effort. The evaluation kit includes a populated, tested ADG2128 printed circuit board. The evaluation board interfaces to the USB port of a PC, or it can be used as a standalone evaluation board. Software is available with the evaluation board that allows the user to easily program the ADG2128 through the USB port.
PAGE 25
5VUSB Figure 36. EVAL-ADG2128EB Schematic, USB Controller Section C13 10UF 0.1UF C3 ADP3303-3.3 8 OUT1 7 IN1 OUT2 IN2 5 SD ERROR GND NR U5 4 J1 USB-MINI-B 1 VBUS 2 DSHIELD 3 D+ 4 IO 5 GND C6 C7 C8 C19 C20 C9 0.1UF R6 75 C21 1 2 6 3 C16 0.1UF C14 10UF +3.3V +3.
PAGE 26
AVSS Rev. D | Page 26 of 28 Figure 37. EVAL-ADG2128EB Schematic, Chip Section Y6_Y7-B Y6_Y7-A Y4_Y5-B Y4_Y5-A Y2_Y3-B Y2_Y3-A Y0_Y1-B Y0_Y1-A X4_X5-B X4_X5-A X2_X3-B X2_X3-A X0_X1-B X0_X1-A A B 4 3 4 3 4 3 4 3 4 3 4 3 4 3 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DGND R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R4 R3 R2 R1 C11 0.
PAGE 27
Data Sheet ADG2128 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 38.
PAGE 28
ADG2128 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05464-0-10/12(D) Rev.