Datasheet

ADG2108 Data Sheet
Rev. B | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
Y2
Y4
Y3
Y6
Y7
Y1
Y0
Y5
NC
V
DD
X9
X8
X7
X6
X5
X4
X1
NC
NC
NC
X3
X2
X0
V
SS
RESET
A1
SCL
A2
A0
SDA
GND
V
L
1
2
3
4
5
6
7
8
32 31 30 29 28
27
26 25
24
23
22
21
20
19
18
17
9 10 11
13 14
15
1612
PIN 1
INDIC
AT
OR
ADG2108
10 × 8
TOP VIEW
(Not to Scale)
05898-003
Exposed Paddle Soldered to V
SS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
SS
Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin
should be tied to GND.
2 to 4, 23 NC No Connect.
5 to 8,
17 to 22
X0 to X9 Can be inputs or outputs.
9 to 16 Y0 to Y7 Can be inputs or outputs.
24 V
DD
Positive Power Supply Input.
25 V
L
Logic Power Supply Input.
26
SDA
Digital I/O. Bidirectional open drain data line. External pull-up resistor required.
27 SCL
Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data
into the device. External pull-up resistor required.
28 A0 Logic Input. Address pin that sets the least significant bit of the 7-bit slave address.
29 A1 Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address.
30 A2 Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address.
31
RESET
Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.
32 GND Ground. Reference point for all circuitry on the ADG2108.
EP
Exposed Pad. It is recommended that the exposed pad be soldered to V
SS
to improve heat dissipation and
crosstalk.