Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches TSSOP 20

4 Ω R

, Triple/Quad SPDT

±15 V/+12 V/±5 V iCMOS Switches

ADG1433/ADG1434

Rev. C

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FEATURES

4.7 Ω maximum on resistance @ 25°C

0.5 Ω on resistance flatness

Fully specified at ±15 V/+12 V/±5 V

3 V logic-compatible inputs

Up to 115 mA continuous current per channel

Rail-to-rail operation

Break-before-make switching action

16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages

APPLICATIONS

Relay replacement

Audio and video routing

Automatic test equipment

Data acquisition systems

Temperature measurement systems

Avionics

Battery-powered systems

Communication systems

Medical equipment

GENERAL DESCRIPTION

The ADG1433 and ADG1434 are monolithic industrial CMOS

(iCMOS®) analog switches comprising three independently

selectable single-pole, double-throw (SPDT) switches and

four independently selectable SPDT switches, respectively.

All channels exhibit break-before-make switching action that

prevents momentary shorting when switching channels. An

input on the ADG1433 (LFCSP and TSSOP packages) and

ADG1434 (LFCSP package only) is used to enable or disable

the device. When disabled, all channels are switched off.

The iCMOS modular manufacturing process combines high

voltage, complementary metal-oxide semiconductor (CMOS),

and bipolar technologies. It enables the development of a wide

range of high performance analog ICs capable of 33 V operation

in a footprint that no other generation of high voltage parts has

been able to achieve. Unlike analog ICs using a conventional

CMOS process, iCMOS components can tolerate high supply

voltages while providing increased performance, dramatically

lower power consumption, and reduced package size.

The ultralow on resistance and on resistance flatness of these

switches make them ideal solutions for data acquisition and gain

switching applications, where low distortion is critical. iCMOS

construction ensures ultralow power dissipation, making the parts

ideally suited for portable and battery-powered instruments.

FUNCTIONAL BLOCK DIAGRAMS

IN1 IN2 IN3 EN

S1A

S1B

S3B

S3A

S2B

S2A

LOGIC

ADG1433

SWITCHES SHOWN FOR

A 1 INPUT LOGIC.

06181-001

Figure 1. ADG1433 TSSOP and LFCSP_VQ

S1B

IN1

IN2

S2B

S4A

S4B

IN4

IN3

S3B

S3A

ADG1434

SWITCHES SHOWN FOR

1 INPUT LOGIC.

06181-002

Figure 2. ADG1434 TSSOP

S1A

S1B

S2B

S2A

S4A

S4B

S3B

S3A

ADG1434

06181-101

SWITCHES SHOWN FOR

A 1 INPUT LOGIC.

IN1

IN2 IN3 IN4 EN

LOGIC

Figure 3. ADG1434 LFCSP_VQ

Summary of content (20 pages)

PAGE 1
4 Ω RON, Triple/Quad SPDT ±15 V/+12 V/±5 V iCMOS Switches ADG1433/ADG1434 FUNCTIONAL BLOCK DIAGRAMS ADG1433 S1A D1 S1B S3B D3 S2B S3A D2 S2A LOGIC APPLICATIONS Relay replacement Audio and video routing Automatic test equipment Data acquisition systems Temperature measurement systems Avionics Battery-powered systems Communication systems Medical equipment GENERAL DESCRIPTION IN1 IN2 IN3 EN 06181-001 4.7 Ω maximum on resistance @ 25°C 0.
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ADG1433/ADG1434 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 Thermal Resistance .......................................................................7 General Description ..................................................................
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ADG1433/ADG1434 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.
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ADG1433/ADG1434 Parameter POWER REQUIREMENTS IDD +25°C −40°C to +85°C −40°C to +125°C 1 0.001 1 ±4.5/±16.5 μA typ μA max μA typ μA max μA typ μA max V min/max 40 40 mA max mA max 1 IDD 260 ISS 0.001 475 VDD/VSS Continuous Current per Channel2 ADG1433 ADG1434 1 2 115 100 75 65 Unit Temperature range for Y version: −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. C | Page 4 of 20 Test Conditions/Comments VDD = +16.5 V, VSS = −16.
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ADG1433/ADG1434 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIL or IIH +25°C −40°C to +85°C −40°C to +125°C1 0 to VDD 6 8 0.55 0.82 1.
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ADG1433/ADG1434 ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIL or IIH +25°C −40°C to +85°C −40°C to +125°C1 VSS to VDD 7 9 0.
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ADG1433/ADG1434 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
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ADG1433/ADG1434 14 EN S1B 2 S2B 5 TOP VIEW (Not to Scale) D2 6 13 VSS 12 S3B 11 D3 7 10 S3A IN2 8 9 IN3 S2A S2B 3 D2 4 14 GND ADG1433 TOP VIEW (Not to Scale) S2A 5 S1B 4 ADG1433 06181-003 D1 3 PIN 1 INDICATOR 12 EN 11 VSS 10 S3B 9 D3 NOTES 1. EXPOSED PAD IS TIED TO SUBSTRATE, VSS. Figure 4. ADG1433 TSSOP Pin Configuration 06181-005 D1 1 IN3 7 IN1 S3A 8 GND 13 IN1 16 S1A 16 15 IN2 6 VDD 1 S1A 2 15 VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5.
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D4 S1B 4 17 S4B 16 VDD ADG1434 VSS 5 GND TOP VIEW (Not to Scale) 6 S2B 7 D2 8 15 NC 14 S3B 13 D3 9 12 S3A IN2 10 11 IN3 S2A NC = NO CONNECT D1 S1B VSS GND S2B 1 2 3 4 5 PIN 1 INDICATOR ADG1434 TOP VIEW (Not to Scale) 15 14 13 12 11 D4 S4B VDD S3B D3 NOTES 1. EXPOSED PAD IS TIED TO SUBSTRATE, VSS. Figure 6.
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ADG1433/ADG1434 TYPICAL PERFORMANCE CHARACTERISTICS 7 VDD = +15V VSS = –15V TA = 25°C 6 ON RESISTANCE (Ω) 4 3 2 1 0 –16.5 VDD VDD VDD VDD VDD = +15V, VSS = –15V = +13.5V, VSS = –13.5V = +12V, VSS = –12V = +10V, VSS = –10V = +16.5V, VSS = –16.5V –12.5 –8.5 –4.5 5 4 3 2 1 –0.5 3.5 7.5 11.5 15.5 SOURCE OR DRAIN VOLTAGE (V) 0 –15 06181-007 ON RESISTANCE (Ω) 5 TA = +25°C TA = +85°C TA = –40°C TA = +125°C –10 –5 0 5 10 15 SOURCE OR DRAIN VOLTAGE (V) 06181-010 6 Figure 11.
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ADG1433/ADG1434 70 1600 ID, IS (ON) + + 1200 IS (OFF) + – 1000 IDD PER CHANNEL TA = 25°C 60 50 800 IDD (µA) 600 40 30 400 20 IS (OFF) – + 200 10 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 06181-013 2 0 10 12 14 200 VDD = +5V 1400 VSS = –5V VBIAS = +4.5V/–4.5V TA = 25°C 150 ID, IS (ON) + + 1200 CHARGE INJECTION (pC) LEAKAGE CURRENTS (pA) 8 Figure 17. IDD vs.
PAGE 12
ADG1433/ADG1434 0 LOAD = 110Ω TA = 25°C 0.09 0.08 –30 0.07 THD + N (%) –40 –50 –60 –70 VDD = +5V, VSS = –5V, VS = +5V p-p 0.06 0.05 0.04 0.03 –80 –90 0.02 –100 0.01 –110 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VDD = +15V, VSS = –15V, VS = +15V p-p 0 10 06181-018 OFF ISOLATION (dB) –20 0.10 VDD = +15V VSS = –15V TA = 25°C 10k 100k Figure 23. THD + N vs. Frequency 0 –20 1k FREQUENCY (Hz) Figure 20. Off Isolation vs.
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ADG1433/ADG1434 TEST CIRCUITS V A D IDS D Figure 26. Off Leakage ID (ON) D NC = NO CONNECT A VD 06181-023 S NC Figure 27. On Leakage VDD VSS VIN 50% 50% VIN 50% 50% VSS VDD SB VS 0.1µF D SA VOUT RL 100Ω IN CL 35pF 90% 90% VOUT tON tOFF 06181-024 GND VIN Figure 28. Switching Timing 0.1µF VDD VSS VDD VSS SB VS 0.1µF VIN D SA VOUT RL 100Ω IN VOUT 80% CL 35pF tBBM GND tBBM 06181-025 VIN Figure 29. Break-Before-Make Delay, tD VDD VSS VDD VSS 0.
PAGE 14
ADG1433/ADG1434 VS VDD VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) SB D NC SA CL 1nF IN VOUT OFF VIN (NORMALLY OPEN SWITCH) VOUT GND VIN ON ΔVOUT QINJ = CL × ΔVOUT 06181-027 0.1µF Figure 31. Charge Injection VDD VDD VSS NC SB SA NETWORK ANALYZER NETWORK ANALYZER VSS VOUT 50Ω VDD SA RL 50Ω 50Ω D SB VS D VIN GND OFF ISOLATION = 20 log VOUT VOUT VS VDD VDD 0.1µF VSS 0.1µF 0.1µF VDD VSS SA SB VOUT VS Figure 34. Channel-to-Channel Crosstalk VSS 0.
PAGE 15
ADG1433/ADG1434 TERMINOLOGY tBBM Off time measured between the 80% point of both switches when switching from one address state to another. RON Ohmic resistance between Terminal D and Terminal S. ΔRON The difference between the RON of any two channels. RFLAT(ON) The difference between the maximum and minimum value of on resistance as measured. VIL Maximum input voltage for Logic 0. VIH Minimum input voltage for Logic 1. IS (Off) Source leakage current when the switch is off.
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ADG1433/ADG1434 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC 0.20 0.09 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 4 9 8 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP 0.30 0.
PAGE 17
ADG1433/ADG1434 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 1.00 0.85 0.80 12° MAX 0.
PAGE 18
ADG1433/ADG1434 NOTES Rev.
PAGE 19
ADG1433/ADG1434 NOTES Rev.