Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches MSOP 8

4 Ω R

, Triple/Quad SPDT

±15 V/+12 V/±5 V iCMOS Switches

Data Sheet

ADG1433/ADG1434

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

4.7 Ω maximum on resistance at 25°C

0.5 Ω on-resistance flatness

Fully specified at ±15 V/+12 V/±5 V

3 V logic-compatible inputs

Up to 115 mA continuous current per channel

Rail-to-rail operation

Break-before-make switching action

16-/20-lead TSSOP and 4 mm × 4 mm LFCSP

APPLICATIONS

Relay replacement

Audio and video routing

Automatic test equipment

Data acquisition systems

Temperature measurement systems

Avionics

Battery-powered systems

Communication systems

Medical equipment

GENERAL DESCRIPTION

The ADG1433 and ADG1434 are monolithic industrial CMOS

(iCMOS®) analog switches comprising three independently

selectable single-pole, double-throw (SPDT) switches and

four independently selectable SPDT switches, respectively.

All channels exhibit break-before-make switching action that

prevents momentary shorting when switching channels. An

input on the ADG1433 (LFCSP and TSSOP) and ADG1434

(LFCSP only) enables or disables the device. When disabled, all

channels are switched off.

The iCMOS modular manufacturing process combines high

voltage, complementary metal-oxide semiconductor (CMOS),

and bipolar technologies. It enables the development of a wide

range of high performance analog ICs capable of 33 V operation

in a footprint that no other generation of high voltage devices

has been able to achieve. Unlike analog ICs using a conventional

CMOS process, iCMOS components can tolerate high supply

voltages while providing increased performance, dramatically

lower power consumption, and reduced package size.

The ultralow on resistance and on resistance flatness of these

switches make them ideal solutions for data acquisition and gain

switching applications, where low distortion is critical. iCMOS

construction ensures ultralow power dissipation, making the

devices ideally suited for portable and battery-powered

instruments.

FUNCTIONAL BLOCK DIAGRAMS

IN1 IN2 IN3 EN

S1A

S1B

S2B

S2A

S3B

S3A

LOGIC

ADG1433

SWITCHES SHOWN FOR

A 1 INPUT LOGIC.

06181-001

Figure 1. ADG1433 TSSOP and LFCSP

S1B

IN1

IN2

S2B

S4A

S4B

IN4

IN3

S3B

S3A

ADG1434

SWITCHES SHOWN FOR

1 INPUT LOGIC.

06181-002

Figure 2. ADG1434 TSSOP

06181-101

S1A

S1B

S2B

S2A

S4A

S4B

S3B

S3A

ADG1434

SWITCHES SHOWN FOR

A 1 INPUT LOGIC.

IN1

IN2 IN3 IN4 EN

LOGIC

Figure 3. ADG1434 LFCSP

Downloaded from Arrow.com.

Summary of content (20 pages)

PAGE 1
4 Ω RON, Triple/Quad SPDT ±15 V/+12 V/±5 V iCMOS Switches ADG1433/ADG1434 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS 4.7 Ω maximum on resistance at 25°C 0.
PAGE 2
ADG1433/ADG1434 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 Thermal Resistance .......................................................................7 General Description .....................................................
PAGE 3
Data Sheet ADG1433/ADG1434 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.
PAGE 4
ADG1433/ADG1434 Parameter POWER REQUIREMENTS IDD Data Sheet +25°C −40°C to +85°C −40°C to +125°C 1 0.001 1 ±4.5/±16.5 µA typ µA max µA typ µA max µA typ µA max V min/max 40 40 mA max mA max 1 IDD 260 ISS 0.001 475 VDD/VSS Continuous Current per Channel2 ADG1433 ADG1434 1 2 115 100 75 65 Temperature range for Y version: −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. E | Page 4 of 20 Downloaded from Arrow.com. Unit Test Conditions/Comments VDD = +16.
PAGE 5
Data Sheet ADG1433/ADG1434 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
PAGE 6
ADG1433/ADG1434 Data Sheet ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 3.
PAGE 7
Data Sheet ADG1433/ADG1434 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
PAGE 8
ADG1433/ADG1434 Data Sheet 13 IN1 14 GND 16 S1A 15 VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 16 GND S1A 2 15 IN1 S1B 2 ADG1433 11 VSS S2B 3 TOP VIEW (Not to Scale) 10 S3B 13 VSS 12 S3B S2B 5 D2 6 11 D3 S2A 7 10 S3A IN2 8 9 IN3 9 D2 4 D3 NOTES 1. THE EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS. Figure 4. ADG1433 TSSOP Pin Configuration 06181-005 TOP VIEW (Not to Scale) IN3 7 S1B 4 S3A 8 EN IN2 6 14 12 EN S2A 5 ADG1433 06181-003 D1 3 D1 1 Figure 5.
PAGE 9
ADG1433/ADG1434 20 IN4 19 S4A D1 3 20 19 18 17 16 IN1 1 S1A 2 S1A IN1 EN IN4 S4A Data Sheet 18 D4 S1B 4 17 S4B VSS 5 ADG1434 GND 6 TOP VIEW (Not to Scale) S2B 7 D1 1 S1B 2 VSS 3 GND 4 S2B 5 16 VDD 15 NIC 14 S3B D2 8 ADG1434 TOP VIEW (Not to Scale) 15 14 13 12 11 D4 S4B VDD S3B D3 6 7 8 9 10 13 D3 11 IN3 NIC = NO INTERNAL CONNECTION. NOTES 1. THE EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS. Figure 6.
PAGE 10
ADG1433/ADG1434 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 7 VDD = +15V VSS = –15V TA = 25°C 6 ON RESISTANCE (Ω) 4 3 2 1 0 –16.5 VDD VDD VDD VDD VDD = +15V, VSS = –15V = +13.5V, VSS = –13.5V = +12V, VSS = –12V = +10V, VSS = –10V = +16.5V, VSS = –16.5V –12.5 –8.5 –4.5 5 4 3 2 1 –0.5 3.5 7.5 15.5 11.5 SOURCE OR DRAIN VOLTAGE (V) 0 –15 06181-007 ON RESISTANCE (Ω) 5 TA = +25°C TA = +85°C TA = –40°C TA = +125°C –10 –5 0 5 15 10 SOURCE OR DRAIN VOLTAGE (V) Figure 8.
PAGE 11
ADG1433/ADG1434 1600 70 VDD = +15V 1400 VSS = –15V VBIAS = +10V/–10V 60 ID, IS (ON) + + 1200 IS (OFF) + – 1000 IDD PER CHANNEL TA = 25°C 50 800 IDD (µA) 600 40 30 400 20 IS (OFF) – + 200 10 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 06181-013 0 2 10 14 12 200 VDD = +5V 1400 VSS = –5V VBIAS = +4.5V/–4.5V TA = 25°C 150 ID, IS (ON) + + 1200 CHARGE INJECTION (pC) LEAKAGE CURRENTS (pA) 8 Figure 17. IDD vs.
PAGE 12
ADG1433/ADG1434 Data Sheet 0 LOAD = 110Ω TA = 25°C 0.09 0.08 –30 0.07 THD + N (%) –40 –50 –60 –70 VDD = +5V, VSS = –5V, VS = +5V p-p 0.06 0.05 0.04 0.03 –80 –90 0.02 –100 0.01 –110 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VDD = +15V, VSS = –15V, VS = +15V p-p 0 10 06181-018 OFF ISOLATION (dB) –20 0.10 VDD = +15V VSS = –15V TA = 25°C 10k 100k Figure 23. THD + N vs. Frequency 0 –20 1k FREQUENCY (Hz) Figure 20. Off Isolation vs.
PAGE 13
Data Sheet ADG1433/ADG1434 TEST CIRCUITS V S D IDS 06181-021 VS Figure 25. On Resistance IS (OFF) A S D ID (OFF) A VD 06181-022 VS Figure 26. Off Leakage ID (ON) S NIC D A NIC = NO INTERNAL CONNECTION. 06181-023 VD Figure 27. On Leakage VDD 0.1µF VSS VDD VIN 50% 50% VIN 50% 50% VSS SB VS 0.1µF D SA VOUT RL 100Ω IN CL 35pF 90% 90% VOUT tON tOFF 06181-024 GND VIN Figure 28. Switching Timing 0.1µF VDD VSS VDD VSS SB VS 0.
PAGE 14
ADG1433/ADG1434 Data Sheet 0.1µF VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) SB D NIC SA CL 1nF IN VOUT OFF VIN (NORMALLY OPEN SWITCH) VOUT GND VIN ON ∆VOUT QINJ = CL × ∆VOUT 06181-027 VS VDD NIC = NO INTERNAL CONNECTION. Figure 31. Charge Injection VDD NETWORK ANALYZER VSS NIC SB SA VSS 0.1µF 0.1µF 0.1µF VDD IN VDD VSS 0.
PAGE 15
Data Sheet ADG1433/ADG1434 TERMINOLOGY tBBM Off time measured between the 80% point of both switches when switching from one address state to another. RON Ohmic resistance between Terminal D and Terminal S. ∆RON The difference between the RON of any two channels. RFLAT(ON) The difference between the maximum and minimum value of on resistance as measured. VIL Maximum input voltage for Logic 0. VIH Minimum input voltage for Logic 1. IS (Off) Source leakage current when the switch is off.
PAGE 16
ADG1433/ADG1434 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.35 0.30 0.25 0.65 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 2.60 2.50 SQ 2.40 9 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.
PAGE 17
Data Sheet ADG1433/ADG1434 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 0.
PAGE 18
ADG1433/ADG1434 Data Sheet NOTES Rev. E | Page 18 of 20 Downloaded from Arrow.com.
PAGE 19
Data Sheet ADG1433/ADG1434 NOTES Rev. E | Page 19 of 20 Downloaded from Arrow.com.
PAGE 20
ADG1433/ADG1434 Data Sheet NOTES ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06181-0-8/16(E) Rev. E | Page 20 of 20 Downloaded from Arrow.com.