Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LFCSP 8 WD

2.1 Ω On Resistance, ±15 V/+12 V/±5 V

iCMOS SPDT Switch

ADG1419

Rev. 0

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FEATURES

2.1 Ω on resistance

0.5 Ω maximum on resistance flatness at 25°C

Up to 390 mA continuous current

Fully specified at +12 V, ±15 V, ±5 V

No V

supply required

3 V logic-compatible inputs

Rail-to-rail operation

8-lead MSOP and 8-lead 3 mm × 2 mm LFCSP packages

APPLICATIONS

Automatic test equipment

Data acquisition systems

Battery-powered systems

Relay replacements

Sample-and-hold systems

Audio signal routing

Video signal routing

Communication systems

FUNCTIONAL BLOCK DIAGRAM

ADG1419 LFCSP

DECODER

SWITCHES SHOWN FOR A LOGIC 0 INPUT.

08485-001

Figure 1. 8-Lead LFCSP Functional Block Diagram

ADG1419 MSOP

SWITCHES SHOWN FOR A LOGIC 0 INPUT.

08485-002

Figure 2. 8-Lead MSOP Functional Block Diagram

GENERAL DESCRIPTION

The ADG1419 is a monolithic iCMOS® device containing a

single-pole/double-throw (SPDT) switch. An EN input on the

LFCSP package is used to enable or disable the device. When

disabled, all channels are switched off.

The iCMOS (industrial CMOS) modular manufacturing process

combines high voltage, complementary metal-oxide semiconductor

(CMOS) and bipolar technologies. It enables the development

of a wide range of high performance analog ICs capable of 33 V

operation in a footprint that no other generation of high voltage

parts has achieved. Unlike analog ICs using conventional CMOS

processes, iCMOS components can tolerate high supply voltages

while providing increased performance, dramatically lower

power consumption, and reduced package size.

The on resistance profile is very flat over the full analog input

range ensuring excellent linearity and low distortion when

switching audio signals. The iCMOS construction ensures

ultralow power dissipation, making the part ideally suited

for portable and battery-powered instruments.

Each switch conducts equally well in both directions when on

and has an input signal range that extends to the supplies. In the

off condition, signal levels up to the supplies are blocked. The

ADG1419 exhibits break-before-make switching action for use

in multiplexer applications.

PRODUCT HIGHLIGHTS

1. 2.4 Ω maximum on resistance at 25°C.

2. Minimum distortion.

3. 3 V logic-compatible digital inputs: V

INH

= 2.0 V, V

INL

= 0.8 V.

4. No V

logic power supply required.

5. 8-lead MSOP and 8-lead, 3 mm × 2 mm LFCSP packages.

Summary of content (16 pages)

PAGE 1
2.1 Ω On Resistance, ±15 V/+12 V/±5 V iCMOS SPDT Switch ADG1419 FEATURES FUNCTIONAL BLOCK DIAGRAM 2.1 Ω on resistance 0.5 Ω maximum on resistance flatness at 25°C Up to 390 mA continuous current Fully specified at +12 V, ±15 V, ±5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 8-lead MSOP and 8-lead 3 mm × 2 mm LFCSP packages ADG1419 LFCSP SA D SB EN IN SWITCHES SHOWN FOR A LOGIC 0 INPUT. 08485-001 DECODER Figure 1.
PAGE 2
ADG1419 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 Thermal Resistance .......................................................................7 Functional Block Diagram ..............................................................
PAGE 3
ADG1419 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.
PAGE 4
ADG1419 Parameter POWER REQUIREMENTS IDD 25°C −40°C to +85°C −40°C to +125°C 0.002 1.0 IDD, 8-Lead MSOP 58 IDD, 8-Lead LFCSP 120 95 190 ISS 0.002 1.0 ±4.5/±16.5 VDD/VSS 1 Unit μA typ μA max μA typ μA max μA typ μA max μA typ μA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD Ground = 0 V Guaranteed by design, not subject to production test.
PAGE 5
ADG1419 Parameter Channel-to-Channel Crosstalk 25°C −60 −3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 95 0.3 32 72 123 −40°C to +85°C −40°C to +125°C MHz typ dB typ pF typ pF typ pF typ 0.001 1.0 IDD, 8-Lead MSOP 58 95 IDD, 8-Lead LFCSP 120 190 5/16.
PAGE 6
ADG1419 Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 25°C −40°C to +85°C −40°C to +125°C 495 560 355 390 335 365 Test Conditions/Comments RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 25 RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 3 V; see Figure 26 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 kΩ
PAGE 7
ADG1419 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. Table 6. Thermal Resistance Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D (Pulsed at 1 ms, 10% Duty-Cycle Maximum) 8-Lead MSOP (4-Layer Board) 8-Lead LFCSP Continuous Current per Channel, S or D Operating Temperature Range Industrial Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free 1 Rating 35 V −0.3 V to +25 V +0.
PAGE 8
ADG1419 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 SB SA 2 ADG1419 7 VSS GND 3 TOP VIEW (Not to Scale) 6 IN D 1 5 EN NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. ADG1419 GND 3 TOP VIEW (Not to Scale) VDD 4 08485-003 VDD 4 SA 2 8 SB 7 VSS 6 IN 5 NC NC = NO CONNECT Figure 3. 8-Lead LFCSP Pin Configuration 08485-004 D 1 Figure 4. 8-Lead MSOP Pin Configuration Table 7. 8-Lead LFCSP Pin Function Descriptions Table 9. 8-Lead MSOP Pin Function Descriptions Pin No.
PAGE 9
ADG1419 TYPICAL PERFORMANCE CHARACTERISTICS 4.0 3.5 VDD = +15V VSS = –15V TA = 25°C 3.5 3.0 3.0 ON RESISTANCE (Ω) ON RESISTANCE (Ω) VDD = +10V VSS = –10V VDD = +12V VSS = –12V 2.5 VDD = +13.5V VSS = –13.5V 2.0 TA = +125°C 2.5 TA = +85°C 2.0 TA = +25°C 1.5 TA = –40°C 1.0 1.5 VDD = +16.5V VSS = –16.5V –11.5 –6.5 –1.5 3.5 VS, VD (V) 8.5 13.5 0 –15 –5 0 5 10 15 VS, VD (V) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, ±15 V Dual Supply Figure 5.
PAGE 10
ADG1419 70 60 IDD PER CHANNEL TA = 25°C 80 70 50 60 40 ID (OFF) – + ID (OFF) + – ID, IS (ON) + + IS (OFF) + – IS (OFF) – + ID, IS (ON) – – 30 20 IDD (µA) LEAKAGE CURRENT (nA) 90 VDD = +15V VSS = –15V VBIAS = ±10V 50 40 VDD = +15V VSS = –15V VDD = +12V VSS = 0V 30 20 10 VDD = +5V VSS = –5V 10 0 20 40 60 80 100 120 TEMPERATURE (°C) –10 08485-019 0 0 2 4 12 14 16 TA = 25°C 400 VDD = +5V VSS = –5V 300 50 CHARGE INJECTION (pC) LEAKAGE CURRENT (nA) 10 500 VDD = 12V VSS
PAGE 11
ADG1419 0.06 RL = 110Ω TA = 25°C 0 0.05 VDD = +5V VSS = –5V VS = 5V p-p 0.04 –40 THD + N (%) OFF ISOLATION (dB) –20 TA = 25°C VDD = +15V VSS = –15V –60 0.03 0.02 –80 VDD = +15V VSS = –15V VS = 10V p-p 0.01 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 08485-006 10k 15k 20k Figure 20. THD + N vs.
PAGE 12
ADG1419 TEST CIRCUITS V ID (ON) S D NC S D A 08485-021 VS Figure 22. On Resistance A Figure 24. On Leakage ID (OFF) S D A VS 08485-022 IS (OFF) VD NC = NO CONNECT 08485-023 IDS VD Figure 23. Off Leakage VDD VSS VDD VS 0.1µF 50% 50% VIN 50% 50% VSS SB D VOUT SA RL 300Ω IN VIN VIN CL 35pF 90% 90% VOUT GND tON tOFF 08485-024 0.1µF Figure 25. Switching Times, tON and tOFF 0.1µF VS VDD VSS VDD VSS SB 0.
PAGE 13
ADG1419 VDD VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) ON SB VS D VOUT SA CL 1nF IN VIN OFF NC VIN (NORMALLY OPEN SWITCH) VOUT GND ΔVOUT QINJ = CL × ΔVOUT 08485-027 0.1µF Figure 28. Charge Injection VDD VSS 0.1µF VDD NETWORK ANALYZER VSS NC SA SB 0.1µF VDD NC 50Ω 50Ω SA IN VS SB VS D D VIN RL 50Ω VOUT VOUT VIN GND 08485-028 GND OFF ISOLATION = 20 log VOUT VS INSERTION LOSS = 20 log Figure 29.
PAGE 14
ADG1419 TERMINOLOGY tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. See Figure 27. IDD The positive supply current. ISS The negative supply current. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. See Figure 27. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S.
PAGE 15
ADG1419 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 6° 0° 0.40 0.25 0.80 0.55 0.40 0.23 0.09 100709-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 33. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 1.75 1.65 1.50 2.00 BSC 5 3.00 BSC 8 1.90 1.80 1.65 EXPOSED PAD 0.20 MIN 4 INDEX AREA 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 0.30 0.25 0.