Datasheet

ADG1414 Data Sheet
Rev. A | Page 8 of 20
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2 (see Figure 2).
V
DD
= 4.5 V to 16.5 V; V
SS
= −16.5 V to 0 V; V
L
= 2.7 V to 5.5 V or V
DD
(whichever is less); GND = 0 V; all specifications T
MIN
to T
MAX
,
unless otherwise noted.
1
Table 6.
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
t
1
2
20 ns min SCLK cycle time
t
2
9 ns min SCLK high time
t
3
9 ns min SCLK low time
t
4
5 ns min
SYNC
to SCLK active edge setup time
t
5
5 ns min Data setup time
t
6
5 ns min Data hold time
t
7
5 ns min SCLK active edge to
SYNC
rising edge
t
8
15 ns min Minimum
SYNC
high time
t
9
5 ns min
SYNC
rising edge to next SCLK active edge ignored
t
10
5
ns min
SCLK active edge to
SYNC
falling edge ignored
t
11
3
40 ns max SCLK rising edge to SDO valid
t
12
15 ns min Minimum
RESET
pulse width
1
Guaranteed by design and characterization, not production tested.
2
Maximum SCLK frequency is 50 MHz at V
DD
= 4.5 V to 16.5 V; V
SS
= −16.5 V to 0 V, V
L
= 2.7 V to 5.5 V or V
DD
(whichever is less); GND = 0 V.
3
Measured with the 1 kΩ pull-up resistor to V
L
and 20 pF load. t
11
determines the maximum SCLK frequency in daisy-chain mode.
Timing Diagrams
t
4
t
3
SCLK
DIN
t
1
t
2
t
5
t
6
t
7
t
8
DB7
t
9
t
10
SYNC
t
12
RESET
DB0
08497-002
Figure 2. Serial Write Operation