Datasheet

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9.5 Ω R

±15 V/+12 V/±5 V iCMOS

Serially-Controlled Octal SPST Switches

Data Sheet

ADG1414

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FEATURES

SPI interface

Supports daisy-chain mode

9.5 Ω on resistance @ 25°C

1.6 Ω on-resistance flatness

Fully specified at ±15 V, +12 V, ±5 V

3 V logic-compatible inputs

Rail-to-rail operation

24-lead TSSOP and 24-lead 4 mm × 4 mm LFCSP

APPLICATIONS

Automatic test equipment

Data acquisition systems

Battery-powered systems

Sample-and-hold systems

Audio signal routing

Video signal routing

Communication systems

FUNCTIONAL BLOCK DIAGRAM

SDO

INPUT SHIFT

SCLK

DIN SYNC RESET/V

ADG1414

08497-001

Figure 1.

GENERAL DESCRIPTION

The ADG1414 is a monolithic complementary metal-oxide

semiconductor (CMOS) device containing eight independently

selectable switches designed on an industrial CMOS (iCMOS®)

process. iCMOS is a modular manufacturing process combining

high voltage CMOS and bipolar technologies. iCMOS components

can tolerate high supply voltages while providing increased perfor-

mance, dramatically lower power consumption, and reduce the

package size.

The ADG1414 is a set of octal SPST (single-pole, single-throw)

switches controlled via a 3-wire serial interface. On resistance is

closely matched between switches and is very flat over the full

signal range. Each switch conducts equally well in both direc-

tions and the input signal range extends to the supplies.

Data is written to these devices in the form of eight bits; each

bit corresponds to one channel.

The ADG1414 utilizes a versatile 3-wire serial interface that

operates at clock rates of up to 50 MHz and is compatible with

standard SPI, QSPI™, MICROWIRE™, and DSP interface

standards. The output of the shift register, SDO, enables a

number of these parts to be daisy chained.

On power-up, all switches are in the off condition, and the

internal registers contain all zeros.

PRODUCT HIGHLIGHTS

1. 50 MHz serial interface.

2. 9.5 Ω on resistance.

3. 1.6 Ω on-resistance flatness.

4. 24-lead TSSOP and 4 mm × 4 mm LFCSP packages.

Summary of content (20 pages)

PAGE 1
9.5 Ω RON ±15 V/+12 V/±5 V iCMOS Serially-Controlled Octal SPST Switches ADG1414 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface Supports daisy-chain mode 9.5 Ω on resistance @ 25°C 1.
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ADG1414 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution................................................................................ 10 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ......................... 11 Functional Block Diagram ..............................................................
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Data Sheet ADG1414 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) +25°C −40°C to +85°C VSS to VDD 9.5 11.5 0.55 14 1 1.6 1.9 1.5 1.7 2.15 2.3 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.05 ±1 Drain Off Leakage, ID (Off ) ±0.15 ±0.05 ±0.15 ±0.1 ±0.
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ADG1414 Data Sheet Parameter POWER REQUIREMENTS IDD −40°C to +85°C +25°C −40°C to +125°C 0.001 1 IL Inactive 0.3 IL Active @ 30 MHz 0.26 1 IL Active @ 50 MHz 0.3 0.35 0.5 0.55 0.42 ISS 0.001 1 ±4.5/±16.5 VDD/VSS 1 Unit µA typ µA max µA typ µA max mA typ mA max mA typ mA max µA typ µA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.
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Data Sheet Parameter DYNAMIC CHARACTERISTICS1 tON ADG1414 +25°C −40°C to +85°C −40°C to +125°C 220 240 46 46 Test Conditions/Comments ns typ ns max ns typ ns max pC typ RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 M
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ADG1414 Data Sheet ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to VDD, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) +25°C −40°C to +85°C VSS to VDD 21 25 0.6 29 1.3 5.2 6.4 1.7 1.9 7.3 7.6 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.02 ±1 Drain Off Leakage, ID (Off ) ±0.15 ±0.02 ±0.15 ±0.05 ±0.
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Data Sheet Parameter POWER REQUIREMENTS IDD ADG1414 +25°C −40°C to +85°C −40°C to +125°C 0.001 1 IL Inactive 0.3 IL Active @ 30 MHz 0.26 1 IL Active @ 50 MHz ISS 0.3 0.35 0.5 0.55 0.42 0.001 1 ±4.5/±16.5 VDD/VSS 1 Unit µA typ µA max µA typ µA max mA typ mA max mA typ mA max µA typ µA max V min/max Test Conditions/Comments VDD = +5.5 V, VSS = −5.
PAGE 8
ADG1414 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 6.
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Data Sheet ADG1414 t1 SCLK 8 t8 t3 t4 16 t9 t2 t7 SYNC t5 t6 DIN DB7 DB0 DB0 DB7 INPUT WORD FOR DEVICE N + 1 INPUT WORD FOR DEVICE N t11 DB0 DB31 UNDEFINED INPUT WORD FOR DEVICE N Figure 3. Daisy-Chain Timing Diagram Rev.
PAGE 10
ADG1414 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs1 Digital Inputs1 Continuous Current, Sx or Dx Pins Peak Current, Sx or Dx (Pulsed at 1 ms, 10% Duty Cycle Max) TSSOP Package LFCSP Package Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb free Time at Peak Temperature 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V −0.
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Data Sheet ADG1414 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCLK 1 22 SDO GND 4 21 VSS D2 8 20 S8 GND S1 D1 S2 D2 S3 19 D8 18 S7 17 D7 S3 9 16 S6 D3 10 15 D6 S4 11 14 S5 D4 12 13 D5 1 2 3 4 5 6 PIN 1 INDICATOR ADG1414 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VSS S8 D8 S7 D7 S6 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 4.
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ADG1414 TSSOP 24 N/A 1 1 Data Sheet Pin No. LFCSP 21 Mnemonic SYNC EP Exposed Pad Description Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch condition. Exposed Pad. Exposed pad tied to the substrate, VSS. N/A means not applicable. Rev.
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Data Sheet ADG1414 TYPICAL PERFORMANCE CHARACTERISTICS 16 18 VDD = +10V VSS = –10V VDD = +13.5V VSS = –13.5V 14 15 VDD = +12V VSS = –12V ON RESISTANCE (Ω) ON RESISTANCE (Ω) 12 10 8 6 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V 4 12 TA = +125°C TA = +85°C 9 TA = +25°C 6 TA = –40°C 3 2 –1.5 4.5 1.5 7.5 10.5 13.5 16.5 VS, VD (V) 0 –15 08497-006 0 –16.5 –13.5 –10.5 –7.5 –4.5 Figure 6. On Resistance as a Function of VD (VS), Dual Supply 15 25 ON RESISTANCE (Ω) VDD = +5.
PAGE 14
ADG1414 Data Sheet 2.5 500 IDD PER LOGIC INPUT TA = 25°C VL = 5.5V ID, IS (ON) – – 1.5 400 ID (OFF) –+ IS (OFF) +– 1.0 ID, IS (ON) ++ 0.5 IDD (µA) LEAKAGE CURRENT (nA) VDD = +15V VSS = –15V 2.0 VBIAS = +10/–10V 0 300 200 –0.5 IS (OFF) –+ –1.0 100 ID (OFF) +– –1.5 40 60 80 100 120 TEMPERATURE (°C) 0 0.5 1.0 80 CHARGE INJECTION (pC) 2.0 1.5 ID, IS (ON) – – 1.0 ID (OFF) –+ IS (OFF) +– 0 –1.0 20 40 60 80 100 120 TEMPERATURE (°C) 4.0 4.5 5.
PAGE 15
Data Sheet 0 0.20 LOAD = 110Ω 0.18 TA = 25°C TA = 25°C VDD = +15V VSS = –15V 0.16 VDD = +5V, VSS = –5V, VS = +5V p-p 0.14 –40 THD + N (%) OFF ISOLATION (dB) –20 ADG1414 –60 0.12 0.10 0.08 VDD = +15V, VSS = –15V, VS = +10V p-p –80 0.06 0.04 –100 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 08497-019 –120 1k 0 5000 Figure 18. Off Isolation vs. Frequency 15,000 20,000 Figure 21. THD + N vs. Frequency, 15 V Dual Supply 0 0 TA = 25°C VDD = +15V VSS = –15V –0.
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ADG1414 Data Sheet TEST CIRCUITS IDS V1 A D ID (OFF) A NC VD VS VDD 0.1µF S NETWORK ANALYZER 0.1µF VDD 50Ω IN VS VS D D RL 50Ω GND VOUT VIN OFF ISOLATION = 20 log VOUT VS INSERTION LOSS = 20 log Figure 26. Off Isolation VDD RL 50Ω VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 28. Insertion Loss VSS 0.1µF 0.1µF VDD VSS 0.1µF 0.
PAGE 17
Data Sheet ADG1414 VDD VSS 0.1µF 0.1µF VSS S VOUT D VS INPUT LOGIC RL 300Ω CL 35pF SYNC 50% 50% 90% 90% VOUT GND tON tOFF 08497-029 VDD Figure 30. Switching Times 3V SYNC RS VDD VSS VDD VSS S D QINJ = CL × ∆VOUT INPUT LOGIC ∆VOUT SWITCH OFF SWITCH ON Figure 31. Charge Injection Rev.
PAGE 18
ADG1414 Data Sheet TERMINOLOGY IDD The positive supply current. CD, CS (On) The on switch capacitance, measured with reference to ground. ISS The negative supply current. CIN The digital input capacitance. VD (VS) The analog voltage on Terminal Dx or Terminal Sx. tON The delay between applying the digital control input and the output switching on. See Figure 30. RON The ohmic resistance between Terminal Dx and Terminal Sx. Δ RON The difference between the RON of any two channels.
PAGE 19
Data Sheet ADG1414 THEORY OF OPERATION The ADG1414 is a set of serially controlled, octal SPST switches. Each of the eight bits of the 8-bit write corresponds to one switch of the device. A Logic 1 in the particular bit position turns the switch on, whereas a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches turned on.
PAGE 20
ADG1414 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.75 0.60 0.45 8° 0° 0.20 0.09 SEATING PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 32. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 3.75 BSC SQ 1 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD 6 13 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.