Datasheet

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Low Capacitance, Triple/Quad SPDT

±15 V/+12 V i

CMOS™ Switches

ADG1233/ADG1234

Rev. B

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FEATURES

1.5 pF off capacitance

0.5 pC charge injection

33 V supply range

120 Ω on resistance

Fully specified at ±15 V/+12 V

3 V logic-compatible inputs

Rail-to-rail operation

Break-before-make switching action

16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP

Typical power consumption (<0.03 μW)

APPLICATIONS

Audio and video routing

Automatic test equipment

Data acquisition systems

Battery-powered systems

Sample-and-hold systems

Communication systems

GENERAL DESCRIPTION

The ADG1233 and ADG1234 are monolithic iCMOS analog

switches comprising three independently selectable single-pole,

double throw SPDT switches and four independently selectable

SPDT switches, respectively.

All channels exhibit break-before-make switching action

preventing momentary shorting when switching channels.

input on the ADG1233 and ADG1234 is used to

enable or disable the device. When disabled, all channels are

switched off.

FUNCTIONAL BLOCK DIAGRAMS

ADG1233

S1B

S1A

S2A

IN2IN1 IN3

S2B

S3A

S3B

SWITCHES SHOWN FOR A LOGIC 1 INPUT

05743-001

LOGIC

Figure 1.

SWITCHES SHOWN FOR A LOGIC 1 INPUT

05743-038

ADG1234

S1B

S1A

S2A

IN2IN1 IN3

S2B

S4B

S4A

S3A

S3B

LOGIC

IN4

Figure 2.

The iCMOS (industrial-CMOS) modular manufacturing process

combines a high voltage complementary metal-oxide semi-

conductor (CMOS) and bipolar technologies. It enables the

development of a wide range of high performance analog ICs

capable of 33 V operation in a footprint that no other generation of

high voltage parts has been able to achieve. Unlike analog ICs

using conventional CMOS processes, iCMOS components can

tolerate high supply voltages while providing increased perfor-

mance, dramatically lowered power consumption, and reduced

package size.

The ultralow capacitance and charge injection of these multiplexers

make them ideal solutions for data acquisition and sample-and-

hold applications, where low glitch and fast settling are required.

Fast switching speed coupled with high signal bandwidth make the

parts suitable for video signal switching. iCMOS construction

ensures ultralow power dissipation, making the parts ideally

suited for portable and battery-powered instruments.

PRODUCT HIGHLIGHTS

1. 1.5 pF off capacitance (±15 V supply).

2. 0.5 pC charge injection.

3. 3 V logic-compatible digital input, V

= 2.0 V, V

= 0.8 V.

4. 16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.

Summary of content (16 pages)

PAGE 1
Low Capacitance, Triple/Quad SPDT ±15 V/+12 V i CMOS™ Switches ADG1233/ADG1234 FEATURES FUNCTIONAL BLOCK DIAGRAMS 1.5 pF off capacitance 0.5 pC charge injection 33 V supply range 120 Ω on resistance Fully specified at ±15 V/+12 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP Typical power consumption (<0.
PAGE 2
ADG1233/ADG1234 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 General Description ..............................................................
PAGE 3
ADG1233/ADG1234 SPECIFICATIONS DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.
PAGE 4
ADG1233/ADG1234 Parameter POWER REQUIREMENTS IDD +25°C Y Version 1 −40°C to +85°C −40°C to +125°C 0.002 1.0 IDD 260 475 ISS 0.002 1.0 ISS 0.002 VDD/VSS 1 2 1.0 ±5/±16.5 Temperature range for the Y version: −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. B | Page 4 of 16 Unit μA typ μA max μA typ μA max μA typ μA max μA typ μA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.
PAGE 5
ADG1233/ADG1234 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
PAGE 6
ADG1233/ADG1234 Parameter POWER REQUIREMENTS IDD +25°C Y Version 1 −40°C to +85°C −40°C to +125°C 0.002 1.0 IDD 260 VDD 1 2 475 5/16.5 Temperature range for the Y version: −40°C to +125°C Guaranteed by design, not subject to production test. Rev. B | Page 6 of 16 Unit μA typ μA max μA typ μA max V min/max Test Conditions/Comments VDD = 13.
PAGE 7
ADG1233/ADG1234 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Range Automotive Temperature Range (Y Version) Storage Temperature Range Junction Temperature TSSOP, θJA, Thermal Impedance LFCSP, θJA, Thermal Impedance Reflow Soldering Peak Temperature, Pb-Fee 1 Rating 35 V −0.3 V to +25 V +0.
PAGE 8
ADG1233/ADG1234 ADG1233 14 EN S1B 4 13 VSS D1 1 S2B 5 TOP VIEW (Not to Scale) 12 S3B S1B 2 D2 6 11 D3 S2A 7 10 S3A IN2 8 9 IN3 S2B 3 S4B 16 VDD GND 6 15 EN S2B 7 14 S3B VSS 5 ADG1234 TOP VIEW (Not to Scale) D2 8 13 D3 S2A 9 12 S3A IN2 10 11 IN3 D1 S1B VSS GND S2B 1 2 3 4 5 PIN 1 INDICATOR ADG1234 TOP VIEW (Not to Scale) 15 14 13 12 11 D4 S4B VDD S3B D3 Figure 4.
PAGE 9
ADG1233/ADG1234 TERMINOLOGY VDD Most positive supply potential. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. VSS Most negative power supply potential in dual supplies. In single-supply applications, it can be connected to ground. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. GND Ground (0 V) reference.
PAGE 10
ADG1233/ADG1234 TYPICAL PERFORMANCE CHARACTERISTICS 200 250 TA = 25°C 180 VDD = +13.5V VSS = –13.5V 200 TA = +125°C 140 ON RESISTANCE (Ω) 120 VDD = +16.5V VSS = –16.5V 100 80 60 0 –18 –15 –12 –9 –6 –3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 TA = –40°C 0 –15 18 Figure 7. On Resistance as a Function of VD (VS ) for Dual Supply –10 –5 0 5 TEMPERATURE (°C) 600 TA = 25°C VDD = 4.5V VSS = –4.5V 500 15 10 Figure 10.
PAGE 11
ADG1233/ADG1234 130 220 VDD = 12V VSS = 0V VBIAS = 1V/10V 180 160 TIME (ns) 30 –20 120 100 80 IS (OFF) + – ID (OFF) + – IS (OFF) – + ID (OFF) – + ID, IS (ON) – – ID, IS (ON) + + 0 20 40 60 80 TEMPERATURE (°C) 100 20 0 –40 120 0 20 40 60 TEMPERATURE (°C) 80 100 120 0 IDD PER CHANNEL TA = 25°C 180 –10 –20 160 OFF ISOLATION (dB) VDD = +15V VSS = –15V 140 120 100 80 60 VDD = +15V VSS = –15V TA = 25°C –30 –40 –50 –60 –70 –80 40 0 2 4 6 05743-006 8 10 LOGIC, INX (V) 12 14 057
PAGE 12
ADG1233/ADG1234 0 5.0 VDD = +15V VSS = –15V TA = 25°C 4.0 CAPACITANCE (pF) –10 –15 3.0 2.5 DRAIN OFF 2.0 1.5 SOURCE OFF 1.0 05743-013 –20 –25 10k SOURCE/DRAIN ON 3.5 100k 1M 10M 100M FREQUENCY (Hz) 1G 05743-009 ON RESPONSE (dB) –5 VDD = 12V VSS = 0V TA = 25°C 4.5 0.5 0 10G 0 2 4 8 12 10 Figure 22. Capacitance vs. Source Voltage for Single Supply Figure 19. On Response vs. Frequency 10 5.0 LOAD = 10kΩ TA = 25°C VDD = +5V VSS = –5V TA = 25°C 4.
PAGE 13
ADG1233/ADG1234 TEST CIRCUITS V S D IDS 05743-020 VS Figure 24. On Resistance A S ID (OFF) D A VS 05743-021 IS (OFF) VD Figure 25. Off Leakage ID (ON) D NC = NO CONNECT A VD 05743-022 S NC Figure 26. On Leakage VDD VSS VDD VS 0.1µF 50% 50% VIN 50% 50% VSS SxB D SxA VOUT RL 300Ω INx VIN VIN CL 35pF 90% VOUT GND tON 90% tOFF 05743-023 0.1µF Figure 27. Switching Timing VS VDD VSS VDD VSS SxB VIN D SxA VOUT RL 300Ω INx VIN 0.
PAGE 14
ADG1233/ADG1234 0.1µF VDD VSS VDD VSS 0.1µF 3V VS S1A 0V S1B tOFF (EN) ADG1233 VO D1 EN VIN 50Ω 50% 50% RL 300Ω GND CL 35pF VO 0.9VO 0.9VO OUTPUT 0V 05743-025 IN3 IN2 IN1 ENABLE DRIVE (VIN) tON (EN) Figure 29. Enable Delay, tON (EN), tOFF (EN) VDD VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) ON SxB VS VOUT SxA CL 1nF INx VIN OFF NC D VIN (NORMALLY OPEN SWITCH) VOUT GND ΔVOUT QINJ = CL × ΔVOUT 05743-026 0.1µF Figure 30. Charge Injection VDD VDD VSS 0.
PAGE 15
ADG1233/ADG1234 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.
PAGE 16
ADG1233/ADG1234 4.00 BSC SQ 1.00 0.85 0.80 3.75 BSC SQ 0.75 0.60 0.50 9 4 5 0.25 MIN 1.95 BSC 0.05 MAX 0.02 NOM SEATING PLANE 1 2.25 2.10 SQ 1.95 8 0.80 MAX 0.65 TYP 0.35 0.30 0.25 PIN 1 INDICATOR 16 13 12 0.65 BSC TOP VIEW 12° MAX (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 072808-A PIN 1 INDICATOR 0.60 MAX 0.