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Table Of Contents

Low Capacitance, Low Charge Injection,

±15 V/12 V iCMOS SPDT in SOT-23

ADG1219

Rev. A

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ADG1219

DECODER

IN EN

FEATURES

<0.5 pC charge injection over full signal range

2.5 pF off capacitance

Low leakage; 0.6 nA maximum @ 85°C

120 Ω on resistance

Fully specified at +12 V, ±15 V

No V

supply required

3 V logic-compatible inputs

Rail-to-rail operation

8-lead SOT-23 package

APPLICATIONS

Automatic test equipment

Data acquisition systems

Battery-powered systems

Sample-and-hold systems

Audio/video signal routing

Communication systems

FUNCTIONAL BLOCK DIAGRAM

06575-001

SWITCHES SHOWN FO

A LOGIC 0 INPUT

0.5

–0.5

–15 15

06575-033

INPUT VOLTAGE (V)

CHARGE INJECTION (pC)

Figure 1.

GENERAL DESCRIPTION

The ADG1219 is a monolithic iCMOS® device containing an

SPDT switch. An EN input is used to enable or disable the

device. When disabled, all channels are switched off. When on,

each channel conducts equally well in both directions and has

an input signal range that extends to the supplies. Each switch

exhibits break-before-make switching action.

The iCMOS (industrial CMOS) modular manufacturing

process combines high voltage complementary metal-oxide

semiconductor (CMOS) and bipolar technologies. It enables the

development of a wide range of high performance analog ICs

capable of 33 V operation in a footprint that no other generation

of high voltage parts has been able to achieve. Unlike analog ICs

using conventional CMOS processes, iCMOS components can

tolerate high supply voltages while providing increased perfor-

mance, dramatically lower power consumption, and reduced

package size.

The ultralow capacitance and exceptionally low charge injection

of these multiplexers make them ideal solutions for data acquisi-

tion and sample-and-hold applications, where low glitch and

fast settling are required. Figure 2 shows that there is minimum

charge injection over the entire signal range of the device.

iCMOS construction also ensures ultralow power dissipation,

making the parts ideally suited for portable and battery-

powered instruments.

= 25ºC

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

= +15V

= –15V

= +12V

= 0V

= +5V

= –5V

–10 –5 0 5 10

Figure 2. Charge Injection vs. Input Voltage

Summary of content (16 pages)

PAGE 1
Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS SPDT in SOT-23 ADG1219 FEATURES FUNCTIONAL BLOCK DIAGRAM <0.5 pC charge injection over full signal range 2.5 pF off capacitance Low leakage; 0.6 nA maximum @ 85°C 120 Ω on resistance Fully specified at +12 V, ±15 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 8-lead SOT-23 package ADG1219 SA D SB IN EN SWITCHES SHOWN FOR A LOGIC 0 INPUT 06575-001 DECODER Figure 1.
PAGE 2
ADG1219 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram ..............................................................
PAGE 3
ADG1219 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.
PAGE 4
ADG1219 Parameters POWER REQUIREMENTS IDD 25°C B Version 1 −40°C to +85°C −40°C to +125°C 0.001 1.0 IDD 140 190 ISS 0.001 1.0 ±5/±16.5 VDD/VSS 1 2 Unit μA typ μA max μA typ μA max μA typ μA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD |VDD | = |VSS| Temperature range for B version is −40°C to +125°C. Guaranteed by design; not subject to production test.
PAGE 5
ADG1219 Parameters CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 25°C 2.9 3.7 5 5.8 8.5 11 B Version 1 −40°C to +85°C −40°C to +125°C 0.001 1.0 IDD 140 VDD 1 2 190 5/16.5 Temperature range for B version is −40°C to +125°C. Guaranteed by design; not subject to production test. Rev.
PAGE 6
ADG1219 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 8-Lead SOT-23, θJA Thermal Impedance Reflow Soldering Peak Temperature, Pb Free 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.
PAGE 7
ADG1219 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EN 1 VDD 2 8 ADG1219 IN SA TOP VIEW 6 D (Not to Scale) VSS 4 5 SB 7 NC = NO CONNECT 06575-003 GND 3 Figure 3. SOT-23 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic EN 2 3 4 5 6 7 8 VDD GND VSS SB D SA IN Description Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the IN logic input determines which switch is turned on.
PAGE 8
ADG1219 TYPICAL PERFORMANCE CHARACTERISTICS 200 250 TA = 25°C 180 VDD = 13.5V VSS = –13.5V 200 TA = +125°C 140 ON RESISTANCE (Ω) 120 VDD = 16.5V VSS = –16.5V 100 80 60 100 TA = –40°C 0 –18 –15 –12 –9 –6 –3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 0 –15 18 Figure 4. On Resistance as a Function of VD (VS) for Dual Supply –10 –5 0 5 TEMPERATURE (°C) 600 TA = 25°C VDD = 4.5V VSS = –4.5V 500 10 15 Figure 7.
PAGE 9
ADG1219 0.6 0.5 IS(OFF)+– VDD = 12V VSS = 0V VBIAS = 1V/10V 0.5 IS(OFF)–+ 0.4 ID, IS(ON)++ 0.3 ID, IS(ON)– – 0.2 0.1 0 –0.1 VDD = +15V VSS = –15V 0.2 0.1 0 VDD = 12V VSS = 0V –0.1 –0.2 –0.3 0 20 40 60 80 100 VDD = +5V VSS = –5V –0.4 –0.5 –15 120 –10 –5 TEMPERATURE (°C) 06574-041 06575-031 –0.2 –0.3 TA = 25ºC 0.3 ID(OFF)–+ CHARGE INJECTION (pC) LEAKAGE (nA) 0.4 ID(OFF)+– 0 5 10 15 INPUT VOLTAGE (V) Figure 10.
PAGE 10
ADG1219 0 –20 8 VDD = 15V VSS = –15V TA = 25ºC 7 SOURCE/DRAIN ON 6 CAPACITANCE (pF) CROSSTALK (dB) –30 –40 –50 –60 –70 –80 5 DRAIN OFF 4 SOURCE OFF 3 2 –90 –110 10k 100k 1M 10M 100M VDD = 15V VSS = –15V TA = 25ºC 1 06575-026 –100 0 –15 1G –10 –5 FREQUENCY (Hz) 5 10 15 Figure 19. Capacitance vs. Source Voltage for Dual Supply 9 0 VDD = 15V VSS = –15V TA = 25ºC 8 SOURCE/DRAIN ON 7 –4 CAPACITANCE (pF) INSERTION LOSS (dB) 0 SOURCE VOLTAGE (V) Figure 16. Crosstalk vs.
PAGE 11
ADG1219 0 –10 –20 VDD = +15V VSS = –15V V p-p = 0.63V TA = 25°C NO DECOUPLING CAPS ON –40 –50 –60 DECOUPLING CAPS ON –70 –80 06575-034 ACPSRR (dB) –30 –90 –100 100k 1M 10M 100M FREQUENCY (Hz) Figure 22. ACPSRR vs. Frequency Rev.
PAGE 12
ADG1219 TEST CIRCUITS VDD V S VSS 0.1µF 0.1µF D VDD IDS NC 06575-011 VS NETWORK ANALYZER VSS SB SA IN 50Ω 50Ω VS D VIN RL 50Ω GND INSERTION LOSS = 20 log IS (OFF) A S D ID (OFF) VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 27. Channel-to-Channel Crosstalk A 06575-012 VDD VS VD VSS 0.1µF 0.1µF NETWORK ANALYZER Figure 24. Off Leakage VOUT VDD VSS SA RL 50Ω SB ID (ON) NC = NO CONNECT VD R 50Ω IN VS A D GND CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 25.
PAGE 13
ADG1219 VDD VSS VDD D SA VOUT RL 300Ω IN VIN VIN 50% 50% VIN 50% 50% VSS SB VS 0.1µF CL 35pF 90% VOUT GND tON 90% tOFF 06575-014 0.1µF Figure 30. Switching Times 0.1µF VDD VSS VDD VSS SB VS 0.1µF VIN D SA VOUT RL 300Ω IN VOUT CL 35pF 80% tBBM VIN tBBM 06575-015 GND Figure 31. Break-Before-Make Time Delay VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) SB VS SA IN VIN GND ON OFF NC D VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT ΔVOUT Figure 32.
PAGE 14
ADG1219 TERMINOLOGY tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. IDD The positive supply current. ISS The negative supply current. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S.
PAGE 15
ADG1219 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 PIN 1 INDICATOR 3.00 2.80 2.60 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-BA 121608-A 1.30 1.15 0.90 Figure 33.