Datasheet

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Low Capacitance, Low Charge Injection,

±15 V/+12 V

CMOS Quad SPST Switches

Data Sheet

ADG1211/ADG1212/ADG1213

Rev. B

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FEATURES

1 pF off capacitance

2.6 pF on capacitance

<1 pC charge injection

33 V supply range

120 Ω on resistance

Fully specified at ±15 V, +12 V

No V

supply required

3 V logic-compatible inputs

Rail-to-rail operation

16-lead TSSOP and 16-lead LFCSP

Typical power consumption: <0.03 µW

APPLICATIONS

Automatic test equipment

Data acquisition systems

Battery-powered systems

Sample-and-hold systems

Audio signal routing

Video signal routing

Communication systems

GENERAL DESCRIPTION

The ADG1211/ADG1212/ADG1213 are monolithic complemen-

tary metal-oxide semiconductor (CMOS) devices containing

four independently selectable switches designed on an iCMOS®

(industrial CMOS) process. iCMOS is a modular manufacturing

process combining high voltage CMOS and bipolar technologies.

It enables the development of a wide range of high performance

analog ICs capable of 33 V operation in a footprint that no

previous generation of high voltage parts has been able to achieve.

Unlike analog ICs using conventional CMOS processes, iCMOS

components can tolerate high supply voltages while providing

increased performance, dramatically lower power consumption,

and reduced package size.

The ultralow capacitance and charge injection of these switches

make them ideal solutions for data acquisition and sample-and-

hold applications, where low glitch and fast settling are required.

Fast switching speed coupled with high signal bandwidth make

the parts suitable for video signal switching.

FUNCTIONAL BLOCK DIAGRAM

IN1

IN2

IN3

IN4

ADG1211

SWITCHES SHOWN FOR A LOGIC 1 INPUT

IN1

IN2

IN3

IN4

ADG1212

IN1

IN2

IN3

IN4

ADG1213

04778-001

Figure 1.

iCMOS construction ensures ultralow power dissipation,

making the parts ideally suited for portable and battery-

powered instruments.

The ADG1211/ADG1212/ADG1213 contain four independent

single-pole/single-throw (SPST) switches. The ADG1211 and

ADG1212 differ only in that the digital control logic is inverted.

The ADG1211 switches are turned on with Logic 0 on the

appropriate control input, while Logic 1 is required for the

ADG1212. The ADG1213 has two switches with digital control

logic similar to that of the ADG1211; the logic is inverted on

the other two switches. The ADG1213 exhibits break-before-

make switching action for use in multiplexer applications.

Each switch conducts equally well in both directions when on

and has an input signal range that extends to the supplies. In the

off condition, signal levels up to the supplies are blocked.

PRODUCT HIGHLIGHTS

1. Ultralow capacitance.

2. <1 pC charge injection.

3. 3 V logic-compatible digital inputs: V

= 2.0 V, V

= 0.8 V.

4. No V

logic power supply required.

5. Ultralow power dissipation: <0.03 µW.

6. 16-lead TSSOP and 3 mm × 3 mm LFCSP packages.

Summary of content (16 pages)

PAGE 1
FUNCTIONAL BLOCK DIAGRAM FEATURES 1 pF off capacitance 2.6 pF on capacitance <1 pC charge injection 33 V supply range 120 Ω on resistance Fully specified at ±15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead LFCSP Typical power consumption: <0.
PAGE 2
ADG1211/ADG1212/ADG1213 Data Sheet TABLE OF CONTENTS Specifications..................................................................................... 3 Terminology .......................................................................................8 Dual Supply ................................................................................... 3 Typical Performance Characteristics ..............................................9 Single Supply ......................................................
PAGE 3
Data Sheet ADG1211/ADG1212/ADG1213 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) 25°C Y Version 1 −40°C to +85°C −40°C to +125°C VDD to VSS 120 190 2.5 6 20 57 230 260 10 11 72 79 Unit Test Conditions/Comments V Ω typ Ω max Ω typ VS = ±10 V, IS = −1 mA; see Figure 20 VDD = +13.
PAGE 4
ADG1211/ADG1212/ADG1213 Parameter POWER REQUIREMENTS IDD 25°C Data Sheet Y Version 1 −40°C to +85°C −40°C to +125°C 0.001 1.0 IDD 220 380 ISS 0.001 1.0 ISS 0.001 VDD/VSS 1 2 1.0 ±4.5/±16.5 Temperature range for Y version is −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. B | Page 4 of 16 Unit µA typ µA max µA typ µA max µA typ µA max µA typ µA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.
PAGE 5
Data Sheet ADG1211/ADG1212/ADG1213 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
PAGE 6
ADG1211/ADG1212/ADG1213 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance (4-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance Reflow Soldering Peak Temperature, Pb free 1 Rating 35 V −0.3 V to +25 V +0.
PAGE 7
Data Sheet ADG1211/ADG1212/ADG1213 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN2 S1 1 D1 2 15 D2 VSS 2 S1 3 14 S2 VSS 4 GND 5 S4 6 D4 IN4 12 NC 11 S3 7 10 D3 8 9 IN3 TOP VIEW NC = NO CONNECT Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 14 IN2 NC = NO CONNECT Figure 3. LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. LFCSP 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 9 S3 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 2.
PAGE 8
ADG1211/ADG1212/ADG1213 Data Sheet TERMINOLOGY IDD The positive supply current. CD, CS (On) The on switch capacitance, measured with reference to ground. ISS The negative supply current. CIN The digital input capacitance. VD (VS) The analog voltage on Terminals D and S. tON The delay between applying the digital control input and the output switching on. See Figure 23. RON The ohmic resistance between D and S.
PAGE 9
Data Sheet ADG1211/ADG1212/ADG1213 TYPICAL PERFORMANCE CHARACTERISTICS 200 250 VDD = +15V VSS = –15V TA = +25°C 180 VDD = +13.5V VSS = –13.5V 200 140 ON RESISTANCE (Ω) 120 100 VDD = +15V VSS = –15V 80 VDD = +16.5V VSS = –16.5V 60 40 TA = +125°C 150 TA = +85°C 100 04778-008 50 20 0 –18 –15 –12 –9 –6 –3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 0 –15 18 Figure 4. On Resistance as a Function of VD (VS) for Dual Supply –10 –5 0 5 SOURCE OR DRAIN VOLTAGE (V) 10 15 Figure 7.
PAGE 10
ADG1211/ADG1212/ADG1213 Data Sheet 0.30 200 VDD = 12V VSS = 0V VBIAS = 1V/10V 0.25 180 12V SS TON 160 0.20 140 TIME (ns) LEAKAGE (nA) ID, IS (ON) 0.15 0.10 IS (OFF) 0.05 120 15V DS TON 100 80 12V SS TOFF 60 0 40 –0.10 0 20 40 60 80 TEMPERATURE (°C) 100 15V DS TOFF 20 0 –40 120 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 13. TON/TOFF Times vs. Temperature Figure 10.
PAGE 11
Data Sheet ADG1211/ADG1212/ADG1213 0 –5 3.0 VDD = +15V VSS = –15V TA = +25°C SOURCE/DRAIN ON VDD = +15V VSS = –15V TA = +25°C CAPACITANCE (pF) ATTENUATIOIN (dB) 2.5 –10 –15 –20 2.0 1.5 DRAIN OFF 1.0 –25 100k 1M 10M 100M FREQUENCY (Hz) 1G 0.5 –10 10G –8 –6 –4 04778-031 04778-019 –30 10k SOURCE OFF –2 0 2 VBIAS (V) 4 6 8 10 Figure 18. Capacitance vs. Source Voltage, Dual Supply Figure 16. On Response vs. Frequency 10.00 4.
PAGE 12
ADG1211/ADG1212/ADG1213 Data Sheet TEST CIRCUITS IDS V1 VD Figure 20. On Resistance A VD Figure 22. On Leakage VSS 0.1µF 0.1µF VSS VDD S VS NC = NO CONNECT Figure 21. Off Leakage VDD D VIN ADG1212 50% 50% VIN ADG1211 50% 50% VOUT D CL 35pF RL 300Ω IN 90% VOUT 90% GND tOFF tON Figure 23. Switching Times VDD VSS VSS S1 D1 S2 D2 RL 300Ω IN1, IN2 CL 35pF RL 300Ω VOUT2 CL 35pF VOUT1 VOUT1 50% 90% 90% 0V 90% VOUT2 90% 0V ADG1213 tD GND tD Figure 24.
PAGE 13
Data Sheet ADG1211/ADG1212/ADG1213 VSS VDD 0.1µF VDD NETΩORK ANALYZER VSS S 0.1µF VDD 50Ω IN VS VS D D VIN RL 50Ω GND VOUT VIN RL 50Ω 04778-026 GND OFF ISOLATION = 20 LOG VOUT VS INSERTION LOSS = 20 LOG Figure 26. Off Isolation VDD VOUT RL 50W VOUT VOUT ΩITH SΩITCH VOUT ΩITHOUT SΩITCH Figure 28. Bandwidth VSS VDD 0.1µF 0.1µF NETWORK ANALYZER NETΩORK ANALYZER VSS S 50Ω 50Ω IN VSS 0.1µF 04778-028 VDD 0.1µF VDD VSS 0.1µF 0.
PAGE 14
ADG1211/ADG1212/ADG1213 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.60 MAX 3.00 BSC SQ BOTTOM VIEW 13 12 0.45 TOP VIEW 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 0.05 MAX 0.02 NOM 0.30 0.23 0.
PAGE 15
Data Sheet ADG1211/ADG1212/ADG1213 ORDERING GUIDE Model 1 ADG1211YRUZ ADG1211YRUZ-REEL ADG1211YRUZ-REEL7 ADG1211YCPZ-500RL7 ADG1211YCPZ-REEL7 ADG1212YRUZ ADG1212YRUZ-REEL ADG1212YRUZ-REEL7 ADG1212YCPZ-500RL7 ADG1212YCPZ-REEL7 ADG1213YRUZ ADG1213YRUZ-REEL ADG1213YRUZ-REEL7 ADG1213YCPZ-500RL7 ADG1213YCPZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40
PAGE 16
ADG1211/ADG1212/ADG1213 Data Sheet NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04778-0-8/12(B) Rev.