Datasheet
Data Sheet ADF4360-9
Rev. C | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1CPGND
2AV
DD
3AGND
4RF
OUT
A
5RF
OUT
B
6V
VCO
15 DGND
16 REF
IN
17 CLK
18 DATA
14
C
N
13 R
SET
7
V
TUNE
8
AGND
9
L1
11
AGND
12
C
C
10
L2
21
DV
DD
22
AGND
23
LD
24
C
P
20
DIVOUT
19
LE
TOP VIEW
(Not to Scale)
ADF4360-9
07139-003
NOTE
THE EXPOSED PADDLE MUST BE CONNECTED TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AV
DD
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD
must have the same value as DV
DD
.
3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF
OUT
A
VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
5 RF
OUT
B
VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output
Matching section for a description of the various output stages.
6 V
VCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V
VCO
must have the same value as AV
DD
.
7 V
TUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
9 L1
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10 L2
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12 C
C
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the R
SET
pin is 0.6 V. The relationship between I
CP
and R
SET
is
I
CPmax
= 11.75/R
SET
For example, R
SET
= 4.7 kΩ and I
CPmax
= 2.5 mA.
14 C
N
Internal Compensation Node. This pin must be decoupled to V
VCO
with a 10 µF capacitor.
15 DGND Digital Ground.
16 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20 DIVOUT
This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.
Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
21 DV
DD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
DD
must have the same value as AV
DD
.
23
LD
Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
24 CP
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn drives the
internal VCO.
EP Exposed Pad. The exposed pad must be connected to AGND.