Datasheet

Data Sheet ADF4360-9
Rev. C | Page 21 of 24
GSM TEST CLOCK
Figure 30 shows the ADF4360-9 used to generate three different
frequencies at DIVOUT. The frequencies required are 45 MHz,
80 MHz, and 95 MHz. This is achieved by generating 360 MHz,
320 MHz, and 380 MHz and programming the correct A divider
ratio. Because a 50% duty cycle is required, the A/2 DIVOUT
mode is selected. This means that A values of 4, 2, and 2 are
selected, respectively, for each of the output frequencies
previously mentioned.
The low-pass filter was designed using ADIsimPLL™ for a
channel spacing of 1 MHz and an open-loop bandwidth of
40 kHz. Larger PFD frequencies can be used to reduce in-band
noise and, therefore, rms jitter. However, for the purposes of
this example, 1 MHz is used. The measured rms jitter from this
circuit at each frequency is less than 1.5 ps.
Two 21 nH inductors are required for the specified frequency
range. The reference frequency is from a 20 MHz TCXO from
Fox; therefore, an R value of 20 is programmed. Taking into
account the high PFD frequency and its effect on the band
select logic, the band select clock divider is enabled. In this case,
a value of 8 is chosen. A very simple shunt resistor and dc-blocking
capacitor complete the RF output stage. Because these outputs
are not used, they are terminated in 50 Ω resistors. This is
recommended for circuit stability. Leaving the RF outputs
open is not recommended.
The CMOS level output frequency is available at DIVOUT. If
the frequency has to drive a low impedance load, a buffer is
recommended.
SPI-COMPATIBLE SERIAL BUS
ADF4360-9
V
VCO
V
VCO
FOX
801BE-160
20MHz
V
VCO
CPGND AGND DGND L1 L2
RF
OUT
B
RF
OUT
A
CP
DIVOUT
1nF
150pF
21nH470Ω
21nH
470Ω
56pF
2.2nF
51Ω
100pF
100pF
1nF1nF
10µF
4.7kΩ
5.6kΩ
12kΩ
R
SET
C
C
LE
DATA
CLK
REF
IN
C
N
V
TUNE
AV
DD
DV
DD
LD
5
4
7
23
212
6
14
16
17
18
19
13
1
3 8
9
1011
22 15
12
51Ω
51Ω
51Ω
51Ω
V
VDD
LOCK
DETECT
07139-027
20
24
Figure 30.GSM Test Clock