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Clock Generator PLL with Integrated VCO

Data Sheet

ADF4360-9

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FEATURES

Primary output frequency range: 65 MHz to 400 MHz

Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Integer-N synthesizer

Programmable output power level

3-wire serial interface

Digital lock detect

Software power-down mode

APPLICATIONS

System clock generation

Test equipment

Wireless LANs

CATV equipment

GENERAL DESCRIPTION

The ADF4360-9 is an integrated integer-N synthesizer and

voltage-controlled oscillator (VCO). External inductors set the

ADF4360-9 center frequency. This allows a VCO frequency

range of between 65 MHz and 400 MHz.

An additional divider stage allows division of the VCO signal.

The CMOS level output is equivalent to the VCO signal divided

by the integer value between 2 and 31. This divided signal can

be further divided by 2, if desired.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

14-BIT R

COUNTER

CLK

DATA

TUNE

OUT

VCO

DIVOUT

SET

LOCK

DETECT

MULTIPLEXER

MUTE

CHARGE

PUMP

PHASE

COMPARATOR

24-BIT DATA

ADF4360-9

13-BIT B

COUNTER

N = B

VCO

CORE

DIVIDE-BY-A

(2 TO 31)

DIVIDE-BY-2

OUTPUT

STAGE

24-BIT

FUNCTION

LATCH

REF

AGND DGND CPGND

07139-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Clock Generator PLL with Integrated VCO ADF4360-9 Data Sheet FEATURES GENERAL DESCRIPTION Primary output frequency range: 65 MHz to 400 MHz Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Software power-down mode The ADF4360-9 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO).
PAGE 2
ADF4360-9 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 10 Applications ....................................................................................... 1 VCO ............................................................................................. 11 General Description ............................................
PAGE 3
Data Sheet ADF4360-9 SPECIFICATIONS AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency B Version Unit Conditions/Comments 10/250 MHz min/MHz max 0.7/AVDD 0 to AVDD 5.0 ±60 V p-p min/V p-p max V max pF max µA max For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave, slew rate > 21 V/µs AC-coupled CMOS-compatible 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.
PAGE 4
ADF4360-9 Parameter Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power5, 8 Output Power Variation VCO Tuning Range VCO NOISE CHARACTERISTICS VCO Phase Noise Performance 9,10 Normalized In-Band Phase Noise 10, 11 In-Band Phase Noise10, 11 RMS Integrated Jitter 12 Spurious Signals Due to PFD Frequency 13 DIVOUT CHARACTERISTICS12 Integrated Jitter Performance (Integrated from 100 Hz to 1 GHz) DIVOUT = 180 MHz DIVOUT = 95
PAGE 5
Data Sheet ADF4360-9 TIMING CHARACTERISTICS 1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
ADF4360-9 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND REFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Lead Temperature, Soldering Reflow 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.
PAGE 7
Data Sheet ADF4360-9 24 23 22 21 20 19 CP LD AGND DVDD DIVOUT LE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADF4360-9 TOP VIEW (Not to Scale) 18 17 16 15 14 13 DATA CLK REFIN DGND CN RSET NOTE THE EXPOSED PADDLE MUST BE CONNECTED TO AGND. 07139-003 VTUNE AGND L1 L2 AGND CC 7 8 9 10 11 12 CPGND AVDD AGND RFOUTA RFOUTB VVCO Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADF4360-9 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –60 –20 –70 –40 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –80 –60 –80 –100 –120 –90 –100 –110 –120 –130 07139-004 –160 1k 10k 100k 1M 07139-007 –140 –140 –150 –160 100 10M –60 –70 –70 –80 PHASE NOISE (dBc/Hz) –90 –100 –110 –120 –130 –100 –110 –120 –130 –140 07139-005 –140 –90 –150 1k 10k 100k 1k 07139-008 PHASE NOISE (dBc/Hz) –80 –150 –160 100 10M 10k 1k 100k 1M 10M FREQUENCY OFFSET (Hz) FREQUENCY OFFSET (Hz)
PAGE 9
Data Sheet ADF4360-9 –60 –70 PHASE NOISE (dBc/Hz) –80 –90 –100 1 –110 –120 C1 FREQUENCY: 90MHz C1 + DUTY: 28.98% C1 PEAK TO PEAK: 1.55V –130 07139-010 07139-013 –140 –150 –160 100 1k 10k 100k 1M CH1 500mV 10M M 2.00ns A CH1 20mV FREQUENCY OFFSET (Hz) Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected, A = 4, Duty Cycle = ~25% Figure 10. DIVOUT Phase Noise, 45 MHz, VCO = 360 MHz, PFD Frequency = 1.6 MHz, Loop Bandwidth = 60 kHz, Jitter = 1.
PAGE 10
ADF4360-9 Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION VP The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches, and SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin at power-down.
PAGE 11
Data Sheet ADF4360-9 The truth table for these bits is shown in Table 5. Figure 22 shows a summary of how the latches are programmed. Note that the test modes latch is used for factory testing and should not be programmed by the user. C2 0 0 1 1 2.5 Data Latch Control R Counter N Counter (B) Test Modes 2.0 1.5 1.0 0.
PAGE 12
ADF4360-9 Data Sheet OUTPUT STAGE DVDD Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock, as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch.
PAGE 13
Data Sheet ADF4360-9 LATCH STRUCTURE Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed.
PAGE 14
COUNTER RESET OUTPUT POWER LEVEL CP THREESTATE PHASE DETECTOR POLARITY CURRENT SETTING 1 CP GAIN CURRENT SETTING 2 MUTE-TILLLD Data Sheet POWERDOWN 1 POWERDOWN 2 RESERVED RESERVED ADF4360-9 DIVOUT CONTROL CORE POWER LEVEL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 RSV CP PDP D3 D2 D1 CR PC2 PC1 RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG PC2 0 0 1 1 CPI6 CPI3 0 0 0 0 1 1 1 1 CPI5 CPI2 0 0 1
PAGE 15
RESERVED RESERVED ADF4360-9 CP GAIN Data Sheet 13-BIT B COUNTER CONTROL BITS 5-BIT DIVOUT DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 RSV B2 B1 RSV A5 A4 A3 A2 A1 RSV CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB1 DB0 C2 (1) C1 (0) THIS BIT IS NOT USED BY THE DEVICE AND IS A DON'T CARE BIT. A5 0 0 0 0 . . . 1 1 1 1 B13 0 0 0 0 . . . 1 1 1 1 B12 0 0 0 0 . . . 1 1 1 1 B11 0 0 0 0 . . . 1 1 1 1 ............ ....
PAGE 16
Data Sheet TEST MODE BIT LOCK DETECT PRECISION RESERVED RESERVED ADF4360-9 BAND SELECT CLOCK ANTIBACKLASH PULSE WIDTH CONTROL BITS 14-BIT REFERENCE COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 ABP2 ABP1 R8 R7 R6 R5 R4 R3 R2 R1 RSV BSC2 BSC1 TMB THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. LDP TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL OPERATION.
PAGE 17
Data Sheet ADF4360-9 POWER-UP Power-Up Sequence The correct programming sequence for the ADF4360-9 after power-up is as follows: 1. R Counter Latch 2. Control Latch 3. N Counter Latch Initial Power-Up Initial power-up refers to programming the part after the application of voltage to the AVDD, DVDD, and VVCO pins. On initial power-up, an interval is required between programming the control latch and programming the N counter latch.
PAGE 18
ADF4360-9 Data Sheet Software Power-Up/Power-Down Charge Pump Currents If the part is powered down via the software (using the control latch) and powered up again without any change to the N counter latch during power-down, the part locks at the correct frequency because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the CN pin, which is <15 ms for 10 µF capacitance. The smaller capacitance of 440 nF on this pin enables lock times of <600 µs.
PAGE 19
Data Sheet ADF4360-9 N COUNTER LATCH R COUNTER LATCH Figure 24 shows the input data format for programming the N counter latch. With (C2, C1) = (0, 1), the R counter latch is programmed. Figure 25 shows the input data format for programming the R counter latch. 5-Bit Divider A5 to A1 program the output divider. The divide range is 2 (00010) to 31 (11111). If unused, this divider should be set to 0. The output or the output divided by 2 is available at the DIVOUT pin.
PAGE 20
ADF4360-9 Data Sheet APPLICATIONS CHOOSING THE CORRECT INDUCTANCE VALUE 12 10 SENSITIVITY (MHz/V) 8 6 4 The lowest center frequency of oscillation possible is approximately 65 MHz, which is achieved using 560 nH inductors. This relationship can be expressed by 2π 9.3 pF(0.9 nH + L EXT ) FREQUENCY (MHz) 600 Analog-to-digital converters (ADCs) require a sampling clock for their operation. Generally, this is provided by TCXO or VCXOs, which can be large and expensive.
PAGE 21
Data Sheet ADF4360-9 Two 21 nH inductors are required for the specified frequency range. The reference frequency is from a 20 MHz TCXO from Fox; therefore, an R value of 20 is programmed. Taking into account the high PFD frequency and its effect on the band select logic, the band select clock divider is enabled. In this case, a value of 8 is chosen. A very simple shunt resistor and dc-blocking capacitor complete the RF output stage. Because these outputs are not used, they are terminated in 50 Ω resistors.
PAGE 22
ADF4360-9 Data Sheet INTERFACING ADSP-21xx Interface The ADF4360 family has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that are clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table.
PAGE 23
Data Sheet ADF4360-9 There are a number of ways to match the VCO output of the ADF4360-9 for optimum operation; the most basic is to use a 51 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series, as shown in Figure 33. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in the circuit in Figure 33 typically gives −9 dBm output power into a 50 Ω load.
PAGE 24
ADF4360-9 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 18 PIN 1 INDICATOR 3.75 BSC SQ 1 0.50 BSC 2.45 2.30 SQ 2.15 EXPOSED PAD 6 13 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.50 0.40 0.30 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.30 0.23 0.18 7 12 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.