Datasheet

ADF4360-8
Rev. A | Page 10 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
04763-016
BUFFER
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
Figure 16. Reference Input Stage
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is re-
ferred to as the B counter. It makes it possible to generate output
frequencies that are spaced only by the reference frequency
divided by
R. The VCO frequency equation is
RfBf
REFIN
VCO
/×=
where:
f
VCO
is the output frequency of the VCO.
B
is the preset divide ratio of the binary 13-bit counter (3 to 8191).
f
REFIN
is the external reference frequency oscillator.
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(
N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 17 is a simpli-
fied schematic. The PFD includes a programmable delay ele-
ment that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function, and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width of
the pulse (see Table 9).
04763-017
PROGRAMMABLE
DELAY
U3
CLR2
Q2D2
U2
CLR1
Q1D1
CHARGE
PUMP
DOWN
UP
HI
HI
U1
ABP1 ABP2
R DIVIDER
N DIVIDER
C
P OUTPU
T
R DIVIDER
N DIVIDER
CP
CPGND
V
P
Figure 17. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 18 shows
the MUXOUT section in block diagram form.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETEC
T
DGND
CONTROLMUX
MUXOUT
DV
DD
04763-018
Figure 18. MUXOUT Circuit