Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADF4360-8BCPZRL7

Integrated Synthesizer and VCO

ADF4360-8

Rev. A

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FEATURES

Output frequency range: 65 MHz to 400 MHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Integer-N synthesizer

Programmable output power level

3-wire serial interface

Digital lock detect

Hardware and software power-down mode

APPLICATIONS

System clock generation

Test equipment

Wireless LANs

CATV equipment

GENERAL DESCRIPTION

The ADF4360-8 is an integrated integer-N synthesizer and

voltage-controlled oscillator (VCO). The ADF4360-8 center

frequency is set by external inductors. This allows a frequency

range of between 65 MHz to 400 MHz.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging from

3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

MUXOUT

VCO

REF

CLK

DATA

AGND DGND CPGND

SET

TUNE

OUT

VCO

CORE

PHASE

COMPARATOR

MUTE

N = B

CHARGE

PUMP

OUTPUT

STAGE

13-BIT B

COUNTER

14-BIT R

COUNTER

24-BIT

FUNCTION

LATCH

24-BIT

DATA REGISTER

MULTIPLEXER

LOCK

DETECT

ADF4360-8

04763-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Integrated Synthesizer and VCO ADF4360-8 FEATURES GENERAL DESCRIPTION Output frequency range: 65 MHz to 400 MHz 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Hardware and software power-down mode The ADF4360-8 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-8 center frequency is set by external inductors.
PAGE 2
ADF4360-8 TABLE OF CONTENTS Specifications..................................................................................... 3 Output Stage................................................................................ 12 Timing Characteristics ................................................................ 5 Latch Structure ........................................................................... 13 Absolute Maximum Ratings............................................................ 6 Power-Up.
PAGE 3
ADF4360-8 SPECIFICATIONS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency B Version Unit Conditions/Comments 10/250 MHz min/max 0.7/AVDD 0 to AVDD 5.0 ±60 V p-p min/max V max pF max µA max For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew rate > 21 V/µs. AC-coupled CMOS-compatible 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.5 2 mA typ mA typ kΩ nA typ % typ % typ % typ 1.5 0.
PAGE 4
ADF4360-8 Parameter Harmonic Content (Third) Output Power5, 7 Output Power5, 8 Output Power Variation VCO Tuning Range NOISE CHARACTERISTICS5 VCO Phase Noise Performance9 Synthesizer Phase Noise Floor10 Phase Noise Figure of Merit10 In-Band Phase Noise11, 12 RMS Integrated Phase Error13 Spurious Signals due to PFD Frequency12, 14 Level of Unlocked Signal with MTLD Enabled B Version −21 −9/0 −14/−9 ±3 1.25/2.5 Unit dBc typ dBm typ dBm typ dB typ V min/max −120 −139 −140 −142 −160 −150 −142 −215 −102 0.
PAGE 5
ADF4360-8 TIMING CHARACTERISTICS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Refer to the Power-Up section for the recommended power-up procedure for this device.
PAGE 6
ADF4360-8 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.
PAGE 7
ADF4360-8 19 LE 20 MUXOUT 22 AGND 21 DVDD 23 CE 24 CP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IDENTIFIER CPGND 1 AVDD 2 18 DATA 17 CLK CN VVCO 6 13 RSET 04763-003 14 CC 12 DGND RFOUTB 5 AGND 11 15 L2 10 TOP VIEW (Not to Scale) REFIN RFOUTA 4 L1 9 16 VTUNE 7 ADF4360-8 AGND 8 AGND 3 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADF4360-8 –40 0 –50 –10 –60 –20 –70 OUTPUT POWER (dB) –80 –90 –100 –110 –120 –30 –40 –50 –60 –70 –84dBc –150 100 1k 10k 100k FREQUENCY OFFSET (Hz) 1M 04763-007 04763-004 –140 –90 –1.1MHz 10M –0.55MHz 65MHz 0.55MHz 1.1MHz Figure 7. Reference Spurs at 65 MHz (1 MHz Channel Spacing, 100 kHz Loop Bandwidth) Figure 4.
PAGE 9
ADF4360-8 0 –70 –30 –40 –50 –60 –70 –110 –115 –120 –125 –135 –109.4dBc/Hz –2kHz –1kHz 160MHz 1kHz 04763-013 –140 04763-010 –90 –145 –150 100 2kHz Figure 10. Close-In Phase Noise at 160 MHz (1 MHz Channel Spacing) 1k 10k 100k FREQUENCY OFFSET (Hz) 1M 10M Figure 13. VCO Phase Noise, 400 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth 0 0 –20 –30 –40 VDD = 3.3V, V VCO = 3.3V ICP = 2.5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 4.
PAGE 10
ADF4360-8 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. VP HI D1 Q1 CHARGE PUMP UP U1 R DIVIDER CLR1 POWER-DOWN CONTROL NC PROGRAMMABLE DELAY 100kΩ SW2 REFIN NC CP U3 TO R COUNTER ABP1 BUFFER ABP2 CLR2 HI D2 Q2 DOWN U2 Figure 16.
PAGE 11
ADF4360-8 MUXOUT can be programmed for one type of lock detect. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. It stays set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle.
PAGE 12
ADF4360-8 OUTPUT STAGE If the outputs are used individually, the optimum output stage consists of a shunt inductor to VDD. Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock, as measured by the digital lock detect circuitry. This is enabled by the Mute-Till-Lock Detect (MTLD) bit in the control latch.
PAGE 13
ADF4360-8 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed. Table 6.
PAGE 14
ADF4360-8 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG COUNTER RESET CP THREESTATE PHASE DETECTOR POLARITY OUTPUT POWER LEVEL CURRENT SETTING 1 CP GAIN CURRENT SETTING 2 MUTE-TILLD POWERDOWN 1 POWERDOWN 2 RESERVED RESERVED Table 7.
PAGE 15
ADF4360-8 CP GAIN RESERVED RESERVED Table 8. N Counter Latch 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV RSV CPG B13 B12 B11 B10 B9 B8 B7 CONTROL BITS RESERVED B6 B5 B4 B3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 B2 B1 RSV RSV RSV RSV RSV RSV C2 (1) C1 (0) THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. B12 0 0 0 0 . . . 1 1 1 1 B11 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... ..
PAGE 16
ADF4360-8 TEST MODE BIT LOCK DETECT PRECISION RESERVED RESERVED Table 9. R Counter Latch BAND SELECT CLOCK ANTIBACKLASH PULSE WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV BSC2 BSC1 TMB THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. LDP ABP2 ABP1 TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL OPERATION. LDP 0 1 BSC1 0 1 0 1 R13 R12 R11 R10 R14 0 0 0 0 . . . 1 1 1 1 ABP2 0 0 1 1 BSC2 0 0 1 1 R14 ABP1 0 1 0 1 ANTIBACKLASH PULSE WIDTH 3.0ns 1.
PAGE 17
ADF4360-8 POWER-UP Power-Up Sequence The correct programming sequence for the ADF4360-8 after power-up is 1. R counter latch 2. Control latch 3. N counter latch Initial Power-Up Initial power-up refers to programming the part after the application of voltage to the AVDD, DVDD, VVCO, and CE pins. On initial power-up, an interval is required between programming the control latch and programming the N counter latch.
PAGE 18
ADF4360-8 Hardware Power-Up/Power-Down Software Power-Up/Power-Down If the part is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, the part locks at the correct frequency, because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the CN pin, which is <15 ms for 10 µF capacitance. The smaller capacitance of 440 nF on this pin enables lock times of <600 µs.
PAGE 19
ADF4360-8 CONTROL LATCH Charge Pump Currents With (C2, C1) = (0,0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. CPI3, CPI2, and CPI1 in the ADF4360 family determine Current Setting 1. Power-Down CPI6, CPI5, and CPI4 determine Current Setting 2. See the truth table in Table 7. DB21 (PD2) and DB20 (PD1) provide programmable powerdown modes.
PAGE 20
ADF4360-8 N COUNTER LATCH R COUNTER LATCH Table 8 shows the input data format for programming the N counter latch. With (C2, C1) = (0, 1), the R counter latch is programmed. Table 9 shows the input data format for programming the R counter latch. Reserved Bits R Counter DB2 to DB7 are spare bits and have been designated as reserved. They should be programmed to 0. R1 to R14 set the counter divide ratio. The divide range is 1 (00...001) to 16383 (111...111).
PAGE 21
ADF4360-8 12 CHOOSING THE CORRECT INDUCTANCE VALUE 10 8 6 4 2 0 The lowest center frequency of oscillation possible is approximately 65 MHz, which is achieved using 560 nH inductors. This relationship can be expressed by FO = 0 2π 9.3 pF(0.9 nH + L EXT ) 450 400 350 300 250 200 150 200 300 400 INDUCTANCE (nH) 04763-025 200 300 400 INDUCTANCE (nH) 500 600 6 10µF FOX 801BE-160 16MHz Figure 22. Output Center Frequency vs.
PAGE 22
ADF4360-8 INTERFACING ADSP-2181 Interface The ADF4360 family has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that have been clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. Figure 26 shows the interface between the ADF4360 family and the ADSP-21xx digital signal processor.
PAGE 23
ADF4360-8 There are a number of ways to match the output of the ADF4360-8 for optimum operation; the most basic is to use a 50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series, as shown in Figure 27. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in the circuit below typically gives −9 dBm output power into a 50 Ω load. VVCO 51Ω The recommended value of this inductor changes with the VCO center frequency.
PAGE 24
ADF4360-8 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ PIN 1 INDICATOR 0.60 MAX TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX PIN 1 INDICATOR 19 18 24 1 *2.45 EXPOSED PAD 2.30 SQ 2.15 (BOTTOMVIEW) 13 12 7 0.80 MAX 0.65 TYP 6 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 30.