Datasheet

Data Sheet ADF4360-7
Rev. D | Page 21 of 28
APPLICATIONS
FREQUENCY GENERATOR
The wide frequency range of the AD4360-7, plus the on-chip
divider, make it an ideal choice for implementing any general
purpose clock generator or LO.
To implement a clock generator in the FM band, it is necessary
to use an external divider. The ADF4007 contains a hardware-
programmable N divider, allowing division ratios of 8, 16, 32,
and 64. This divided-down signal is accessed from the MUX-
OUT pin of the ADF4007.
The minimum frequency that can be fed to the ADF4007 is
500 MHz. Therefore, 2.2 nH inductors were used to set the
fundamental frequency of oscillation at 1 GHz, with a range
from 950 MHz to 1100 MHz.
This allows frequencies as low as 8 MHz and as high as
137 MHz to be generated using a single system. In the circuit
drawn in Figure 23, the ADF4360-7 is being used to generate
1024 MHz, and the ADF4007 is being used to divide by 8. To
provide a channel spacing of 100 kHz, a PFD frequency of
800 kHz is used for the ADF4360-7 PLL. The loop bandwidth
is chosen to be 20 kHz.
The output range of the system in Figure 23 is approximately
120 MHz to 135 MHz. The output phase noise is −104 dBc/Hz
at 1 kHz offset. Using different inductor values allows the
ADF4360-7 to be used to synthesize any different range of
frequencies over the operation of the part (235 MHz to
1800 MHz).
ADF4007
TO LO
PORT
VP
REF
IN
RF
IN
A
M2 M1
CP
R
SET
MUXOUT
PHASE
FREQUENCY
DETECTOR
R COUNTER
÷2
VDD
RF
IN
B
N2
N1
04441-027
SPI COMPATIBLE SERIAL BUS
ADF4360-7
V
VCO
V
VCO
V
VCO
CPGND
AGND DGND
GNDCPGND
L1 L2
RF
OUT
B
RF
OUT
A
FREF
IN
CP
1nF
470pF
2.2nH
2.2nH
220pF
6.8nF
51
Ω
51
Ω
51Ω
4.7k
Ω
100pF
100pF
1nF
1nF
10
µF
4.7kΩ
6.2k
Ω
13k
Ω
R
SET
C
C
LE
DATA
CLK
REF
IN
C
N
V
TUNE
DV
DD
AV
DD
CE
MUXOUT
5
4
24
7
20
23221
6
14
16
17
18
19
13
1
3 8
9
1011
22 15
12
V
DD
V
DD
LOCK
DETECT
CHARGE
PUMP
MUX
N COUNTER
÷
8,
÷
16,
÷
32,
÷
64
Figure 23. Frequency Generator