Datasheet

Data Sheet
ADF4360-4
Rev. B | Page 15 of 24
Table 9. R Counter Latch
DB20
DB19 DB18
DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10 DB9
DB8 DB7
DB6
DB5 DB4
DB3
DB2 DB1 DB0
C2 (0) C1 (1)
R1R2R3R4R5
R7
R8R9
R10R11
R12
R13R14ABP1ABP2LDPTMBBSC1
R6
C
ON
TR
O
L
B
I
TS
BAND
SE
L
EC
T
C
LO
CK
AN
TI
-
B
AC
K
LA
SH
PULSE
WI
D
TH
14-BIT REFERENCE COUNTER
DB21
DB22DB23
LOCK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED RESERVED
BSC2
RSVRSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14 R13 R12 R3 R2
R1 DIVIDE RATIO
..........
00 0
0
0 0
0
0 0 0
0 0 0
0 0 1
.......... 0
1
1 2
.......... 0
1
0 3
.......... 1
0
1 4
.......... .
. .
.
. . .
. . .
.
. .
.......... . .
.
.
.......... . . .
.
.......... 11 1 1
1 1
1
1
1 1
1 1
1
0 0 16380
..........
1 0 1
16381
..........
1 1
0 16382
.......... 1 1
1 16383
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
04438-019
LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0
0 3.0ns
0 1
1.3ns
1
0 6.0ns
1 1 3.0ns
BSC2 BSC1 BAND SELECT CLOCK DIVIDER
0 0 1
0 1 2
1
0 4
1 1 8