Datasheet

ADF4351 Data Sheet
Rev. 0 | Page 8 of 28
Pin No. Mnemonic Description
22 R
SET
Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage
bias at the R
SET
pin is 0.55 V. The relationship between I
CP
and R
SET
is as follows:
I
CP
= 25.5/R
SET
where:
R
SET
= 5.1 kΩ.
I
CP
= 5 mA.
23 V
COM
Internal Compensation Node. Biased at half the tuning range. Place decoupling capacitors to the ground plane
as close to this pin as possible.
24 V
REF
Reference Voltage. Place decoupling capacitors to the ground plane as close to this pin as possible.
25 LD Lock Detect Output Pin. A logic high output on this pin indicates PLL lock. A logic low output indicates loss
of PLL lock.
26 PDB
RF
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27 DGND Digital Ground. Ground return pin for DV
DD
.
28 DV
DD
Digital Power Supply. DV
DD
must have the same value as AV
DD
. Place decoupling capacitors to the ground
plane as close to this pin as possible.
29
REF
IN
Reference Input. This CMOS input has a nominal threshold of AV
DD
/2 and a dc equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30 MUXOUT Multiplexer Output. The multiplexer output allows the lock detect value, the N divider value, or the R counter
value to be accessed externally.
31 SD
GND
Digital Σ-Δ Modulator Ground. Ground return pin for the Σ-Δ modulator.
32 SDV
DD
Power Supply Pin for the Digital Σ-Δ Modulator. SDV
DD
must have the same value as AV
DD
. Place decoupling
capacitors to the ground plane as close to this pin as possible.
EP Exposed Pad Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.