Datasheet

ADF4351 Data Sheet
Rev. 0 | Page 4 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
Minimum RF Output Power
3
−4 dBm Programmable in 3 dB steps
Maximum RF Output Power
3
5 dBm
Output Power Variation ±1 dB
Minimum VCO Tuning Voltage 0.5 V
Maximum VCO Tuning Voltage
2.5
V
NOISE CHARACTERISTICS
VCO Phase Noise Performance VCO noise is measured in open-loop conditions
−89 dBc/Hz 10 kHz offset from 2.2 GHz carrier
−114 dBc/Hz 100 kHz offset from 2.2 GHz carrier
−134 dBc/Hz 1 MHz offset from 2.2 GHz carrier
−148 dBc/Hz 5 MHz offset from 2.2 GHz carrier
−86 dBc/Hz 10 kHz offset from 3.3 GHz carrier
−111 dBc/Hz 100 kHz offset from 3.3 GHz carrier
−134
dBc/Hz
1 MHz offset from 3.3 GHz carrier
−145 dBc/Hz 5 MHz offset from 3.3 GHz carrier
−83 dBc/Hz 10 kHz offset from 4.4 GHz carrier
−110 dBc/Hz 100 kHz offset from 4.4 GHz carrier
−131 dBc/Hz 1 MHz offset from 4.4 GHz carrier
−145
dBc/Hz
5 MHz offset from 4.4 GHz carrier
Normalized Phase Noise Floor
(PN
SYNTH
)
4
PLL loop BW = 500 kHz
−220 dBc/Hz ABP = 6 ns
−221 dBc/Hz ABP = 3 ns
Normalized 1/f Noise (PN
1_f
)
5
10 kHz offset; normalized to 1 GHz
−116
dBc/Hz
ABP = 6 ns
−118 dBc/Hz ABP = 3 ns
In-Band Phase Noise −100 dBc/Hz 3 kHz from 2111.28 MHz carrier
Integrated RMS Jitter
6
0.27 ps
Spurious Signals Due to PFD
Frequency
−80 dBc
Level of Signal with RF Mute Enabled −40 dBm
1
I
CP
is internally modified to maintain constant loop gain over the frequency range.
2
T
A
= 25°C; AV
DD
= DV
DD
= V
VCO
= 3.3 V; prescaler = 8/9; f
REFIN
= 100 MHz; f
PFD
= 25 MHz; f
RF
= 4.4 GHz.
3
Using 50 Ω resistors to V
VCO
, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the
main output.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log f
PFD
. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: PN
SYNTH
= PN
TOT
− 10 log(f
PFD
) − 20 log N.
5
The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f
RF
)
and at a frequency offset (f) is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6
f
REFIN
= 122.88 MHz; f
PFD
= 30.72 MHz; VCO frequency = 4222.56 MHz; RF
OUT
= 2111.28 MHz; N = 137; loop BW = 60 kHz; I
CP
= 2.5 mA; low noise mode. The noise was
measured with an EVAL-ADF4351EB1Z and the Rohde & Schwarz FSUP signal source analyzer.