Datasheet

ADF4350
Rev. A | Page 8 of 32
Pin No. Mnemonic Description
22 R
SET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the R
SET
pin is 0.55 V. The relationship between I
CP
and R
SET
is
SET
CP
R
25.5
I =
where:
R
SET
= 5.1 kΩ
I
CP
= 5 mA
23 V
COM
Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
24 V
REF
Reference Voltage. Decoupling capacitors to the ground plane should be placed as close as possible to this pin.
25 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.
26 PDB
RF
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27 DGND Digital Ground. Ground return path for DV
DD
.
28 DV
DD
Digital Power Supply. This pin should be the same voltage as AV
DD
. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
29 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30 MUXOUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
31 SD
GND
Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.
32 SDV
DD
Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AV
DD
. Decoupling capacitors to
the ground plane are to be placed as close as possible to this pin.
33 EP Exposed Pad.