Datasheet

ADF4350
Rev. A | Page 14 of 32
REGISTER MAPS
07325-011
DB31
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
N16 N15 N14 N13 N12 N11 N10 N9
RESERVED
16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC)
CONTROL
BITS
N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 PR1 P12 P11 P10 P9
12-BIT PHASE VALUE (PHASE) 12-BIT MODULUS VALUE (MOD)
CONTROL
BITS
P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)
CSR
RDIV2
REFERENCE
DOUBLER
CHARGE
PUMP
CURRENT
SETTING
10-BIT R COUNTER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)
CONTROL
BITS
12-BIT CLOCK DIVIDER VALUE
LDP
PD
POLARITY
PD
CP THREE-
STATE
COUNTER
RESET
OUTPUT
POWER
CLK
DIV
MODE
DBR
1
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
2
DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.
RESERVED
LDF
RESERVED
RESERVED
REGISTER 4
VCO POWER
DOWN
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
CONTROL
BITS
8-BIT BAND SELECT CLOCK DIVIDER VALUE
RF OUTPUT
ENABLE
LD PIN
MODE
AUX OUTPUT
ENABLE
AUX OUTPUT
SELECT
MTLD
DIVIDER
SELECT
FEEDBACK
SELECT
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 5
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000000D15D140110000000000000000C3(1)C2(0)C1(1)
CONTROL
BITS
RESERVED
RESERVED
DBB
2
DOUBLE BUFF
RESERVED
RESERVED
DBR
1
DBR
1
DBR
1
DBR
1
DBR
1
AUX
OUTPUT
POWER
RESERVED
RESERVED
RESERVED
PRESCALER
LOW
NOISE AND
LOW SPUR
MODES
MUXOUT
Figure 23. Register Summary