Datasheet

REV. B
ADF4252
–17–
Table VI. Master Register Map
P11
0
1
P12
0 XO ENABLED (REF
OUT
= REF
IN
)
1 XO DISABLED (REF
OUT
= LOGIC LOW)
(REF
OUT
= LOGIC HIGH WHEN IN POWER-DOWN)
P10
0
1
P9
0
1
0 0 0 0 LOGIC LOW
0 0 0 1 IF ANALOG LOCK DETECT
0 0 1 0 IF R DIVIDER OUTPUT
0 0 1 1 IF N DIVIDER OUTPUT
0 1 0 0 RF ANALOG LOCK DETECT
0 1 0 1 RF/IF ANALOG LOCK DETECT
0 1 1 0 IF DIGITAL LOCK DETECT
0 1 1 1 LOGIC HIGH
1 0 0 0 RF R DIVIDER OUTPUT
1 0 0 1 RF N DIVIDER OUTPUT
1 0 1 0 THREE-STATE OUTPUT
1 0 1 1 LOGIC LOW
1 1 0 0 RF DIGITAL LOCK DETECT
1 1 0 1 RF/IF DIGITAL LOCK DETECT
1 1 1 0 LOGIC HIGH
1 1 1 1 LOGIC LOW
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (1)P9P10P11P12M1M2M3M4
CONTROL
BITS
MUXOUT
C3 (0)
XO
DISABLE
POWER-
DOWN
CP THREE-
STATE
COUNTER
RESET
MUXOUT
M1
M2M3
M4
COUNTER RESET
DISABLED
ENABLED
CP THREE-STATE
DISABLED
THREE-STATE
POWER-DOWN
DISABLED
ENABLED
XO DISABLE