Datasheet
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–5–
PIN FUNCTION DESCRIPTIONS
Pin Number
TSSOP Mnemonic Function
1V
DD
1 Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as
close as possible to this pin. V
DD
1 should have a value of between 2.7 V and 5.5 V. V
DD
1 must have
the same potential as V
DD
2.
2V
P
1 Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
1. In systems where
V
DD
1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
3CP
RF
Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
4 DGND
RF
Ground Pin for the RF Digital Circuitry.
5RF
IN
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
6 AGND
RF
Ground Pin for the RF Analog Circuitry.
7FL
O
RF/IF Fastlock Mode.
8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.
9 DGND
IF
Digital Ground for the IF Digital, Interface and Control Circuitry.
10 MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled
Reference Frequency to be accessed externally.
11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
14 R
SET
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
I
R
CP MAX
SET
=
13 5.
So, with R
SET
= 2.7 kΩ, I
CP MAX
= 5 mA for both the RF and IF Charge Pumps.
15 AGND
IF
Ground Pin for the IF Analog Circuitry.
16 IF
IN
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
17 DGND
IF
Ground Pin for the IF Digital, Interface, and Control Circuitry.
18 CP
IF
Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
19 V
P
2 Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
2. In systems where
V
DD
2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
20 V
DD
2 Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. V
DD
2 should have a value of between 2.7 V and 5.5 V. V
DD
2
must have the same potential as V
DD
1.
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DATA
CLK
MUXOUT
DGND
RF
RF
IN
AGND
RF
DGND
IF
REF
IN
FL
O
LE
R
SET
AGND
IF
V
DD
1
V
DD
2
V
P
2
IF
IN
DGND
IF
CP
IF
V
P
1
CP
RF
ADF4210/
ADF4211/
ADF4212/
ADF4213
CP-20
1
2
3
4
5
AGND
RF
FL
O
CP
RF
RF
IN
DGND
RF
V
DD
2
V
P
2
CP
IF
V
P
1
V
DD
1
20 19 18 17 16
15
14
13
12
11
DGND
IF
IF
IN
LE
R
SET
AGND
IF
6 7 8 9 10
REF
IN
DGND
IF
MUXOUT
DATA
CLK
TOP VIEW
(Not to Scale)
ADF4210/
ADF4211/
ADF4212/
ADF4213