Datasheet
ADF4193 Data Sheet
Rev. F | Page 6 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05328-003
1
CMR
2
A
OUT
3
SW3
NOTES:
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
4
A
GND
1
5
RF
IN–
6
RF
IN+
7
AV
DD
1
24
V
P
2
23
R
SET
22
A
GND
2
21
D
GND
3
20
V
P
1
19
LE
18
DATA
17
CLK
8
DV
DD
1
ADF4193
TOP VIEW
9
D
GND
1
10
DV
DD
2
11
REF
IN
12
D
GND
2
13
DV
DD
3
14
SD
GND
15
SDV
DD
16
MUX
OUT
32
V
P
3
31
AIN+
30
CP
OUT+
29
SW1
28
SW
GND
27
SW2
26
CP
OUT–
25
AIN–
PIN 1
INDICATOR
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CMR Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to
three-fifths of V
P
3. Requires a 0.1 µF capacitor to ground.
2 A
OUT
Differential Amplifier Output to Tune the External VCO.
3 SW3 Fast-Lock Switch 3. Closed while SW3 timeout counter is active.
4 A
GND
1 Analog Ground. This is the ground return pin for the differential amplifier and the RF section.
5 RF
IN−
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
6 RF
IN+
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 AV
DD
1 Power Supply Pin for the RF Section. Nominally 3 V. A 100 pF decoupling capacitor to the ground plane should be
placed as close as possible to this pin.
8 DV
DD
1 Power Supply Pin for the N Divider. Should be the same voltage as AV
DD
1. A 0.1 µF decoupling capacitor to ground
should be placed as close as possible to this pin.
9 D
GND
1 Ground Return Pin for DV
DD
1.
10 DV
DD
2 Power Supply Pin for the REF
IN
Buffer and R Divider. Nominally 3 V. A 0.1 µF decoupling capacitor to ground
should be placed as close as possible to this pin.
11 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of
100 kΩ (see Figure 15). This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
12 D
GND
2 Ground Return Pin for DV
DD
2 and DV
DD
3.
13 DV
DD
3 Power Supply Pin for the Serial Interface Logic. Nominally 3 V.
14 SD
GND
Ground Return Pin for the Σ-Δ Modulator.
15 SDV
DD
Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. A 0.1 µF decoupling capacitor to the ground plane
should be placed as close as possible to this pin.
16 MUX
OUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally (see Figure 35).
17 CLK Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
18 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the three LSBs.
20 V
P
1 Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, should be at the same voltage at V
P
2.
A 0.1 µF decoupling capacitor to ground should be placed as close as possible to this pin.
21
D
GND
3
Ground Return Pin for V
P
1.
22 A
GND
2 Ground Return Pin for V
P
2.