Datasheet

ADF4193 Data Sheet
Rev. F | Page 4 of 32
Parameter B Version
1
C Version
2
Unit Test Conditions/Comments
SW1, SW2, and SW3
R
ON
(SW1 and SW2) 65 65 Ω typ
R
ON
SW3 75 75 Ω typ
NOISE CHARACTERISTICS
Output
900 MHz
4
−108 −108 dBc/Hz typ At 5 kHz offset and 26 MHz PFD frequency
1800 MHz
5
−102 −102 dBc/Hz typ At 5 kHz offset and 13 MHz PFD frequency
Phase Noise
Normalized Phase Noise
Floor (PN
SYNTH
)
6
−216 −216 dBc/Hz typ At VCO output with dither off, PLL loop
bandwidth = 500 kHz
Normalized 1/f Noise (PN
1_f
)
7
−110 −110 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz
1
Operating temperature range is from −40°C to +85°C.
2
Operating temperature range is from −40°C to +105°C
3
The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value.
4
f
REF
IN
= 26 MHz; f
STEP
= 200 kHz; f
RF
= 900 MHz; loop bandwidth = 40 kHz.
5
f
REF
IN
= 13 MHz; f
STEP
= 200 kHz; f
RF
= 1800 MHz; loop bandwidth = 60 kHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(f
PFD
). PN
SYNTH
= PN
TOT
− 10 log(f
PFD
) − 20 log(N).
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,
f
RF
, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL™.
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 3 V ± 10%, V
P
1, V
P
2 = 5 V ± 10%, V
P
3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, R
SET
= 2.4 kΩ, dBm referred to
50 Ω, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Limit (B Version)
1
Limit (C Version)
2
Unit Test Conditions/Comments
t
1
10
10
ns min
LE setup time
t
2
10 10 ns min DATA to CLOCK setup time
t
3
10 10 ns min DATA to CLOCK hold time
t
4
15 15 ns min CLOCK high duration
t
5
15 15 ns min CLOCK low duration
t
6
10 10 ns min CLOCK to LE setup time
t
7
15 15 ns min LE pulse width
1
Operating temperature is from −40°C to +85°C.
2
Operating temperature is from −40°C to +105°C.
05238-002
CLK
DATA
DB23
(MSB)
DB22 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
LE
LE
t
2
t
4
t
5
t
3
t
7
t
6
t
1
Figure 2. Timing Diagram