Datasheet

Data Sheet ADF4159
Rev. D | Page 5 of 36
Parameter
1
Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
3
PLL loop BW = 1 MHz
Integer-N Mode −224 dBc/Hz FRAC = 0; see Σ-Δ Modulator Mode section
Fractional-N Mode −217 dBc/Hz
Normalized 1/f Noise (PN
1_f
)
4
−120
dBc/Hz
Measured at 10 kHz offset, normalized
to 1 GHz
Phase Noise Performance
5
At VCO output
12,002 MHz Output
6
−96 dBc/Hz At 50 kHz offset, 100 MHz PFD frequency
1
Operating temperature: −40°C to +125°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(f
PFD
) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4
The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f
RF
)
and at an offset frequency (f) is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5
The phase noise is measured with the EV-ADF4159EB3Z and the Rohde & Schwarz FSUP signal source analyzer.
6
f
REFIN
= 100 MHz; f
PFD
= 100 MHz; offset frequency = 50 kHz; RF
OUT
= 12,002 MHz; N = 120.02; loop bandwidth = 250 kHz.
TIMING SPECIFICATIONS
AV
DD
= V
P
= 2.7 V to 3.45 V, DV
DD
= SDV
DD
= 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, T
A
= T
MIN
to T
MAX
, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at T
MIN
to T
MAX
Unit
Description
t
1
20 ns min LE setup time
t
2
10
ns min
DATA to CLK setup time
t
3
10 ns min DATA to CLK hold time
t
4
25 ns min CLK high duration
t
5
25 ns min CLK low duration
t
6
10 ns min CLK to LE setup time
t
7
20 ns min LE pulse width
Write Timing Diagram
CLK
DATA
LE
DB30
DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTRO
L BIT C1)
t
1
t
2
t
3
t
4
t
5
t
7
t
6
10849-002
DB31 (MSB)
Figure 2. Write Timing Diagram