Datasheet

ADF4159 Data Sheet
Rev. D | Page 34 of 36
SPUR MECHANISMS
The fractional interpolator in the ADF4159 is a third-order Σ-Δ
modulator with a 25-bit fixed modulus (MOD). The Σ-Δ modu-
lator is clocked at the PFD reference rate (f
PFD
), which allows PLL
output frequencies to be synthesized at a channel step resolution
of f
PFD
/CLK
1
. This section describes the various spur mechanisms
that are possible with fractional-N synthesizers and how they
affect the ADF4159.
Fractional Spurs
In most fractional synthesizers, fractional spurs can appear
at the set channel spacing of the synthesizer. In the ADF4159,
these spurs do not appear. The high value of the fixed modulus
in the ADF4159 makes the Σ-Δ modulator quantization error
spectrum look like broadband noise, effectively spreading the
fractional spurs into noise.
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD
frequency can lead to spurs known as integer boundary spurs.
When these frequencies are not integer related (which is the
purpose of a fractional-N synthesizer), spur sidebands appear
on the VCO output spectrum at an offset frequency that corre-
sponds to the beat note, or difference frequency, between an
integer multiple of the PFD and the VCO frequency.
These spurs are called integer boundary spurs because they are
more noticeable on channels close to integer multiples of the PFD,
where the difference frequency can be inside the loop bandwidth.
These spurs are attenuated by the loop filter on channels far from
integer multiples of the PFD.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mecha-
nism is the feedthrough of low levels of on-chip reference switching
noise out through the RF
IN
x pins back to the VCO, resulting in
reference spur levels as high as −90 dBc. Take care in the PCB
layout to ensure that the VCO is well separated from the input
reference to avoid a possible feedthrough path on the board.
Low Frequency Applications
The specification of the RF input is 0.5 GHz minimum; however,
RF frequencies lower than 0.5 GHz can be used if the minimum
slew rate specification of 400 V/µs is met. An appropriate driver—
for example, the ADCMP553—can be used to accelerate the edge
transitions of the RF signal before it is fed back to the ADF4159
RF input.
FILTER DESIGN USING ADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit http://www.analog.com/pll to down-
load the free ADIsimPLL™ software. This software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter archi-
tectures are allowed.
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-24-10) are rectangular.
The printed circuit board (PCB) pad for these lands must be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. Center the land on the pad to ensure
that the solder joint size is maximized.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as this exposed pad. On the PCB, there must be a clearance
of at least 0.25 mm between the thermal pad and the inner edges
of the pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, incor-
porate them into the thermal pad at the 1.2 mm pitch grid. The
via diameter must be between 0.3 mm and 0.33 mm, and the
via barrel must be plated with 1 ounce of copper to plug the via.
Connect the PCB thermal pad to AGND.