Datasheet

Data Sheet ADF4159
Rev. D | Page 33 of 36
FAST LOCK MODE
The ADF4159 can operate in fast lock mode. In this mode, the
charge pump current is boosted and additional resistors are
connected to maintain the stability of the loop.
Fast Lock Timer and Register Sequences
When fast lock mode is enabled (Register R4, DB[20:19]), after
a write to Register R0, the PLL operates in a wide bandwidth
mode for a selected amount of time. Before fast lock is enabled,
the initialization sequence must be performed after the part is
first powered up (see the Initialization Sequence section). The
time in bandwidth mode is set by:
CLK
1
× CLK
2
/ f
PFD
= Time in wide bandwidth
where:
CLK
1
= Register R2, DB[14:3].
CLK
2
= Register R4, DB[18:7].
f
PFD
= the PFD frequency.
Note that the fast lock feature does not work in ramp mode.
Fast Lock Example
In this example, the PLL has f
PFD
of 100 MHz and requires being
in wide bandwidth mode for 12 µs.
CLK
1
× CLK
2
/ f
PFD
= 12 µs
CLK
1
× CLK
2
= (12 × 10
−6
)(100 × 10
6
) = 1200
Therefore, CLK1 = 12 and CLK2 = 100, which results in 12 µs.
Fast Lock Loop Filter Topology
To u se fast lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter must
be reduced to ¼ of its value in wide bandwidth mode. This reduc-
tion is required because the charge pump current is increased
by 16 in wide bandwidth mode, and stability must be ensured.
To further enhance stability and mitigate frequency overshoot
during a frequency change in wide bandwidth mode, Resistor R3
is connected (see Figure 53). During fast lock, the SW1 pin is
shorted to ground, and the SW2 pin is connected to CP (set
Bits DB[20:19] in Register R4 to 01 for fast lock divider).
The following two topologies can be used:
Divide the damping resistor (R1) into two values (R1 and
R1A) that have a ratio of 1:3 (see Figure 53).
Connect an extra resistor (R1A) directly from SW1 (see
Figure 54). The extra resistor must be selected such that the
parallel combination of an extra resistor and the damping
resistor (R1) is reduced to ¼ of the original value of R1.
For both topologies, the ratio R3:R2 must equal 1:4.
10849-047
ADF4159
SW2
SW1
CP
C1
C2
R1
R1A
R3
R2
C3
VCO
Figure 53. Fast Lock Loop Filter Topology 1
10849-048
ADF4159
SW2
SW1
CP
C1
C2
R1
R1A
R3
R2
C3
VCO
Figure 54. Fast Lock Loop Filter Topology 2
For more fast lock topologies, see ADIsimPLL™.