Datasheet

Data Sheet ADF4159
Rev. D | Page 31 of 36
To set up the parabolic ramp mode, follow these steps:
1. Configure one of the following ramp modes:
• Continuous triangular ramp (set Register R3,
Bits DB[11:10] to 01).
• Single ramp burst (set Register R3, Bits DB[11:10]
to 11).
For the continuous triangular ramp, the generated frequency
range is calculated as follows:
Δf = f
DEV
× (Number of Steps + 2) × (Number of Steps + 1)/2
= 132.6 MHz
For the single ramp burst, the generated frequency range is
calculated as follows:
Δf = f
DEV
× (Number of Steps + 1) × Number of Steps/2
= 127.5 MHz
2. Set the timer as described for the linear ramps in the
Timeout Interval section.
3. Activate the parabolic ramp by setting Bit DB28 in
Register R5 to 1.
4. Set the counter reset (Bit DB3 in Register R3) to 1 and then
set it to 0.
To activate the ramp, see the Activating the Ramp section.
Fast Ramp Mode
The ADF4159 is capable of generating a fast ramp. The fast ramp
is a triangular ramp with two different slopes (see Figure 47).
The number of steps, time per step, and deviation per step are
programmable for both the up and down ramps.
FREQUENCY
TIME
10849-038
Figure 47. Fast Ramp Mode
To activate the fast ramp waveform, follow these steps:
1. Select the continuous triangular waveform by setting
Bits DB[11:10] in Register R3 to 01.
2. Enable the fast ramp by setting Bit DB19 in Register R7 to 1.
3. Program the up ramp as follows.
a. Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23
in Register R5 (DEV SEL), and Bit DB23 in Register R6
(STEP SEL) to 0 for Ramp 1.
b. Calculate and program the timer, DEV, DEV_OFFSET,
and the step word as described in the FMCW Radar
Ramp Settings Worked Example section.
4. Program the down ramp as follows.
a. Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23
in Register R5 (DEV SEL), and Bit DB23 in Register R6
(STEP SEL) to 1 for Ramp 2.
b. Calculate and program the timer, DEV, DEV_OFFSET,
and the step word as described in the FMCW Radar
Ramp Settings Worked Example section.
5. Start the ramp by setting Bit DB31 = 1 in Register R0.
Note that the total frequency change of the up and down ramps
must be equal for stability.
RAMP COMPLETE SIGNAL TO MUXOUT
Figure 48 shows the ramp complete signal on MUXOUT.
FREQUENCY
TIME
VOLTAGE
TIME
10849-039
Figure 48. Ramp Complete Signal on MUXOUT
To activate this function, set Bits DB[30:27] in Register R0
to 1111, and set Bits DB[25:21] in Register R4 to 00011.
EXTERNAL CONTROL OF RAMP STEPS
The internal ramp clock can be bypassed and each step can be
triggered by a pulse on the TX
DATA
pin. This allows for more
transparent control of each step. Enable this feature by setting
Bit DB29 in Register R5 to 1.
FREQUENCY
TIME
TX
DATA
RF
OUT
VOLTAGE
TIME
10849-148
Figure 49. External Control of Ramp Steps