Datasheet

Data Sheet ADF4159
Rev. D | Page 25 of 36
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
After powering up the ADF4159, initialize the part by program-
ming the registers in the following sequence:
1. Delay register (R7).
2. Step register (R6). Load the step register twice, first with
STEP SEL = 0 and then with STEP SEL = 1.
3. Deviation register (R5). Load the deviation register twice,
first with DEV SEL = 0 and then with DEV SEL = 1.
4. Clock register (R4). Load the clock register twice, first with
CLK DIV SEL = 0 and then with CLK DIV SEL = 1.
5. Function register (R3).
6. R divider register (R2).
7. LSB FRAC register (R1).
8. FRAC/INT register (R0).
RF SYNTHESIZER WORKED EXAMPLE
The following equation governs how the synthesizer must
be programmed.
RF
OUT
= (INT + (FRAC/2
25
)) × f
PFD
(4)
where:
RF
OUT
is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
The PFD frequency (f
PFD
) equation is
f
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (5)
where:
REF
IN
is the reference frequency input.
D is the RF REF
IN
doubler bit, Bit DB20 in Register R2 (0 or 1).
R is the RF reference division factor (1 to 32).
T is the reference divide-by-2 bit, Bit DB21 in Register R2 (0 or 1).
For example, in a system where a 12.102 GHz RF frequency
output (RF
OUT
) is required and a 100 MHz reference frequency
input (REF
IN
) is available, the frequency resolution is
f
RES
= REF
IN
/2
25
(6)
f
RES
= 100 MHz/2
25
= 2.98 Hz
From Equation 5,
f
PFD
= [100 MHz × (1 + 0)/1] = 100 MHz
12.102 GHz = 100 MHz × (N + FRAC/2
25
)
Calculating the N and FRAC values,
N = int(RF
OUT
/f
PFD
) = 121
FRAC = F
MSB
× 2
13
+ F
LSB
F
MSB
= int(((RF
OUT
/f
PFD
) − N) × 2
12
) = 81
F
LSB
= int(((((RF
OUT
/f
PFD
) − N) × 2
12
) − F
MSB
) × 2
13
) = 7536
where:
F
MSB
is the 12-bit MSB FRAC value in Register R0.
F
LSB
is the 13-bit LSB FRAC value in Register R1.
int() makes an integer of the argument in parentheses.
REFERENCE DOUBLER
The on-chip reference doubler allows the input reference signal to
be doubled. This doubling is useful for increasing the PFD compar-
ison frequency. Doubling the PFD frequency usually improves
the noise performance of the system by 3 dB. It is important to
note that the PFD cannot be operated above 110 MHz due to a
limitation in the speed of the Σ-Δ circuit of the N divider.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast locking applications, a wide loop filter bandwidth is
required for fast frequency acquisition, resulting in increased
integrated phase noise and reduced spur attenuation. Using cycle
slip reduction, the loop bandwidth can be kept narrow to reduce
integrated phase noise and attenuate spurs while still realizing fast
lock times.
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when the
loop bandwidth is narrow compared with the PFD frequency. The
phase error at the PFD inputs accumulates too fast for the PLL to
correct, and the charge pump temporarily pumps in the wrong
direction, slowing down the lock time dramatically. The ADF4159
contains a cycle slip reduction circuit to extend the linear range
of the PFD, allowing faster lock times without loop filter changes.
When the ADF4159 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. This outputs a constant
current to the loop filter or removes a constant current from the
loop filter (depending on whether the VCO tuning voltage must
increase or decrease to acquire the new frequency). The effect is
that the linear range of the PFD is increased. Stability is maintained
because the current is constant and is not a pulsed current.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4159 turns on another charge pump cell. This
continues until the ADF4159 detects that the VCO frequency has
exceeded the desired frequency. It then begins to turn off the
extra charge pump cells one by one until they are all turned off
and the frequency is settled.
Up to seven extra charge pump cells can be turned on. In most
applications, seven cells is enough to eliminate cycle slips alto-
gether, giving much faster lock times.
When Bit DB28 in the R divider register (Register R2) is set to 1,
cycle slip reduction is enabled. Note that a 45% to 55% duty cycle
is needed on the signal at the PFD in order for CSR to operate
correctly. The reference divide-by-2 flip-flop can help to provide
a 50% duty cycle at the PFD. For example, if a 100 MHz reference
frequency is available and the user wants to run the PFD at
10 MHz, setting the R divide factor to 10 results in a 10 MHz PFD
signal that is not 50% duty cycle. By setting the R divide factor
to 5 and enabling the reference divide-by-2 bit, a 50% duty cycle
10 MHz signal can be achieved.