Datasheet
ADF4159 Data Sheet
Rev. D | Page 24 of 36
DELAY REGISTER (R7) MAP
When Bits DB[2:0] are set to 111, the on-chip delay register
(Register R7) is programmed (see Figure 32).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
TX
DATA
Trigger Delay
When Bit DB23 is set to 0, there is no delay before the start of
the ramp when using TX
DATA
to trigger a ramp. When Bit DB23
is set to 1, a delay is enabled before the start of the ramp if the
delayed start is enabled via Bit DB15.
Triangular Delay
When Bit DB22 is set to 1, a delay is enabled between each
section of a triangular ramp, resulting in a clipped ramp. This
setting works only for triangular ramps and when the ramp
delay is activated. When Bit DB22 is set to 0, the delay between
triangular ramps is disabled.
Single Full Triangle
When Bit DB21 is set to 1, the single full triangle function is
enabled. When Bit DB21 is set to 0, this function is disabled.
For more information, see the Waveform Generation section.
TX
DATA
Trigger
When Bit DB20 is set to 1, a logic high on TX
DATA
activates the
ramp. When Bit DB20 is set to 0, this function is disabled.
Fast Ramp
When Bit DB19 is set to 1, the triangular waveform is activated
with two different slopes. This waveform can be used as an alter-
native to the sawtooth ramp because it mitigates the overshoot
at the end of the ramp in a waveform. Fast ramp is achieved by
changing the top frequency to the bottom frequency in a series of
small steps instead of one big step. When Bit DB19 is set to 0, the
fast ramp function is disabled (see the Fast Ramp Mode section).
Ramp Delay Fast Lock
When Bit DB18 is set to 1, the ramp delay fast lock function is
enabled. When Bit DB18 is set to 0, this function is disabled.
Ramp Delay
When Bit DB17 is set to 1, the delay between ramps function is
enabled. When Bit DB17 is set to 0, this function is disabled.
Delay Clock Select
When Bit DB16 is set to 0, the PFD clock is selected as the delay
clock. When Bit DB16 is set to 1, PFD clock × CLK
1
is selected
as the delay clock. (CLK
1
is set by Bits DB[14:3] in Register R2.)
Delayed Start Enable
When Bit DB15 is set to 1, the delayed start is enabled. When
Bit DB15 is set to 0, the delayed start is disabled.
12-Bit Delay Start Word
Bits DB[14:3] determine the delay start word. The delay start
word affects the duration of the ramp start delay.
DB3
1
12-BIT DELAY START WORD
RESERVED
RAMP DELAY FL
D
B30 D
B29
DB28 DB
27 D
B26 D
B25
DB2
4 DB23 DB22 DB21 DB20 D
B19
DB1
8 DB1
7 D
B16 D
B15
DB1
4 DB
13 DB
12 DB11 DB10 DB9
DB8 D
B7 D
B6 DB5
DB4
DB3 D
B2 D
B1 DB0
0 0 0 0
0 0 0 0 0 0TD1
ST1
TR1 F
R1
RD1 D
C1 D
SE1
DS12 DS11 DS10 DS
9 DS
8 DS
7 DS6 DS5 C3(1) C2(1) C1(1)
DS12 DS11
...
DS2 DS1 DELAY START WORD
0 0 ... 0 0 0
0 0 ... 0 1 1
0 0 ... 1 0 2
0 0 ... 1 1 3
. . ... . . .
. . ... . . .
. . ... . . .
1 1 ... 0 0 4092
1 1 ... 0 1 4093
1 1 ... 1 0 4094
1 1 ... 1 1 4095
D
S4 D
S3
D
S1
DS2
DSE1 DEL START EN
0 DISABLED
1 ENABLED
DEL START EN
DEL CLK SEL
RAMP DELAY
DC1 DEL CLK SEL
0 PFD CLK
1 PFD CLK × CLK
1
RD1 RAMP DELAY
FAST RAMP
TX
DATA
TRIGGER
TX
DATA
TRIGGER DELAY
SING FULL TRI
TRI DELAY
FR1
FAST RAMP
TR1 TX
DATA
TRIGGER
ST1
SING FULL TRI
0 DISABLED
1 ENABLED
0 DISABLED
1
0
1
ENABLED
0 DISABLED
1 ENABLED
DISABLED
ENABLED
0
RAMP DELAY FL
0
1
DISABLED
ENABLED
0
TX
DATA
TRIGGER DELAY
0
1
DISABLED
ENABLED
TD1 TRI DELAY
0 DISABLED
1 ENABLED
CONTROL
BITS
10849-027
Figure 32. Delay Register (R7) Map