Datasheet
ADF4159 Data Sheet
Rev. D | Page 22 of 36
DEVIATION REGISTER (R5) MAP
When Bits DB[2:0] are set to 101, the on-chip deviation register
(Register R5) is programmed (see Figure 30).
Reserved Bit
The reserved bit must be set to 0 for normal operation.
TX
DATA
Invert
When Bit DB30 is set to 0, events triggered by TX
DATA
occur
on the rising edge of the TX
DATA
pulse. When Bit DB30 is set
to 1, events triggered by TX
DATA
occur on the falling edge of
the TX
DATA
pulse.
TX
DATA
Ramp Clock
When Bit DB29 is set to 0, the clock divider clock is used to
clock the ramp. When Bit DB29 is set to 1, the TX
DATA
clock
is used to clock the ramp.
Parabolic Ramp
When Bit DB28 is set to 1, the parabolic ramp is enabled. When
Bit DB28 is set to 0, the parabolic ramp is disabled. For more
information, see the Parabolic (Nonlinear) Ramp Mode section.
Interrupt
Bits DB[27:26] determine which type of interrupt is used. This
feature is used for reading back the INT and FRAC value of a
ramp at a given moment in time (a rising edge on the TX
DATA
pin triggers the interrupt). From the INT and FRAC bits, the
frequency can be obtained. After readback, the sweep can continue
or stop at the readback frequency. For more information, see the
Interrupt Modes and Frequency Readback section.
FSK Ramp Enable
When Bit DB25 is set to 1, the FSK ramp is enabled. When
Bit DB25 is set to 0, the FSK ramp is disabled.
Dual Ramp Enable
When Bit DB24 is set to 1, the second ramp is enabled. When
Bit DB24 is set to 0, the second ramp is disabled.
Deviation Select
When Bit DB23 is set to 0, the first deviation word is selected.
When Bit DB23 is set to 1, the second deviation word is selected.
4-Bit Deviation Offset Word
Bits DB[22:19] determine the deviation offset word. The devia-
tion offset word affects the deviation resolution.
16-Bit Deviation Word
Bits DB[18:3] determine the signed deviation word. The
deviation word defines the deviation step.
16-BIT DEVIATION WORD
CONTROL
BITS
00 0 00TR1 I2 I1 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 C3(1) C2(0) C1(1)
I2
I1
INTERRUPT
0 0 INTERRUPT OFF
11
D16 D15 ...
...
...
...
...
...
...
...
...
...
...
...
D2 D1 DEVIATION WORD
00 00 0
00 01 1
00 10 2
00 11 3
11 11 –1
11 10 –2
11 01 –3
1 0 0 0 –32,768
D4 D3
D1
D2
4-BIT DEVIATION
OFFSET WORD
DEV SEL
01
01
DO4 DO3 DO2 DO1 DEV OFFSET WORD
00000
00011
00102
.....
.....
11017
1
11
00
00
08
9
DS1 DEV SEL
0DEV WORD 1
1DEV WORD 2
0DUAL RAMP
0DISABLED
1 ENABLED
0
0DISABLED
1 ENABLED
0FSK RAMP
0 DISABLED
1 ENABLED
0 PARABOLIC RAMP
0DISABLED
1 ENABLED
TR1 TX
DATA
RAMP CLK
0CLK DIV
1TX
DATA
0 1 1 1 32,767
.. .. .
.. .. .
DUAL RAMP
FSK RAMP
RESERVED
PARABOLIC
RAMP
TX
DATA
RAMP
CLK
TX
DATA
INVERT
INTERRUPT
LOAD CHANNEL CONTINUE SWEEP
NOT USED
LOAD CHANNEL STOP SWEEP
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10849-025
TX
DATA
INVERT
Figure 30. Deviation Register (R5) Map