Datasheet

Data Sheet ADF4159
Rev. D | Page 21 of 36
CLOCK REGISTER (R4) MAP
When Bits DB[2:0] are set to 100, the on-chip clock register
(Register R4) is programmed (see Figure 29).
LE SEL
In some applications, it is necessary to synchronize the LE pin
with the reference signal. To do this, Bit DB31 must be set to 1.
Synchronization is done internally on the part.
Σ-Δ Modulator Mode
To completely disable the Σ-Δ modulator, set Bits DB[30:26] to
0b01110, which puts the ADF4159 into integer-N mode, and
the channel spacing becomes equal to the PFD frequency. Both
the 12-bit MSB fractional value (Register R0, DB[14:3]) and the
13-bit LSB fractional value (Register R1, DB[27:15]) must be set
to 0. After writing to Register 4, Register 3 must be written to twice,
to trigger a counter reset. (That is, write Register 3 with DB3 = 1,
then write Register 3 with DB3 = 0.)
All features driven by the Σ-Δ modulator are disabled, such as
ramping, PSK, FSK, and phase adjust.
Disabling the Σ-Δ modulator also removes the fixed +(f
PFD
/2
26
)
offset on the VCO output.
For normal operation, set these bits to 0b00000.
Ramp Status
Bits DB[25:21] provide access to the following advanced
features (see Figure 29):
• Readback to MUXOUT option: the synthesizer frequency
at the moment of interruption can be read back (see the
Interrupt Modes and Frequency Readback section).
• Ramp complete to MUXOUT option: a logic high pulse
is output on the MUXOUT pin at the end of each ramp.
• Charge pump up and charge pump down options: the
charge pump is forced to constantly output up or down
pulses, respectively.
When using the readback to MUXOUT or ramp complete
to MUXOUT option, the MUXOUT bits in Register R0
(Bits DB[30:27]) must be set to 1111.
Clock Divider Mode
Bits DB[20:19] are used to enable Ramp Divider mode or Fast
Lock Divider mode. If neither is being used, set these bits to 0b00.
12-Bit CLK
2
Divider Value
Bits DB[18:7] program the clock divider (the CLK
2
timer) when
the part operates in ramp mode (see the Timeout Interval section).
The CLK
2
timer also determines how long the loop remains in
wideband mode when fast lock mode is used (see the Fast Lock
Mode section).
Clock Divider Select
When Bit DB6 is set to 0, CLK
2
is used as the CLK
2
value for a
standard ramp, such as sawtooth or triangular. When Bit DB6 is
set to 1, CLK
2
is used as the CLK
2
value for the second ramp of
the Fast Ramp or Dual Ramp functions. For more information,
see the
Waveform Deviations and Timing section.
12-BIT CLK
2
DIVIDER VALUE RESERVED
Σ-Δ
MODULATOR MODE
CONTROL
BITS
LS1 S5 S4 S3 S2 S1 R2R3R4R5 R1
R2R3R4R5 R1
C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D12 D11 ... D2 D1 CLK
2
DIVIDER VALUE
0 0 ... 0 0 0
0 0 ... 0 1 1
0 0 ... 1 0 2
0 0 ... 1 1 3
. . ... . . .
. . ... . . .
. . ... . . .
1 1 ... 0 0 4092
1 1 ... 0 1 4093
1 1 ... 1 0 4094
1 1 ... 1 1 4095
C2 C1 CLOCK DIVIDER MODE
0 0 CLOCK DIVIDER OFF
0 1
CS1
0 00
CLK
DIV
MODE
1 0
1 1
LE SEL
LS1 LE SEL
0
1
RAMP STATUS
0 NORMAL OPERATION
1
000 0
00 0
0 0 0
0
100 0 1
1 0
0 01 10
CS1 CLK DIV SEL
0
1
CLK DIV SEL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(1) C2(0) C1(0)
READBACK TO MUXOUT
RAMP COMPLETE TO MUXOUT
CHARGE PUMP UP
CHARGE PUMP DOWN
S2S3S4S5 S1 Σ-Δ MODULATOR MODE
0 NORMAL OPERATION
1
000 0
10 1 0
DISABLED WHEN FRAC = 0
FAST LOCK DIVIDER
RESERVED
RAMP DIVIDER
LE FROM PIN
LE SYNCH WITH REF
IN
LOAD CLK DIV 1
LOAD CLK DIV 2
10849-024
RAMP STATUS
Figure 29. Clock Register (R4) Map