Datasheet

Data Sheet ADF4159
Rev. D | Page 17 of 36
R DIVIDER REGISTER (R2) MAP
When Bits DB[2:0] are set to 010, the on-chip R divider register
(Register R2) is programmed (see Figure 27).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
CSR Enable
When Bit DB28 is set to 1, cycle slip reduction (CSR) is enabled.
Cycle slip reduction is a method for improving lock times. Note
that the signal at the PFD must have a 50% duty cycle for cycle
slip reduction to work. In addition, the charge pump current
setting must be set to its minimum value. For more information,
see the Cycle Slip Reduction for Faster Lock Times section.
The cycle slip reduction feature can be used only when the phase
detector polarity setting is positive (Bit DB6 = 1 in Register R3).
CSR cannot be used if the phase detector polarity setting is nega-
tive (Bit DB6 = 0 in Register R3).
Charge Pump Current Setting
Bits DB[27:24] set the charge pump current (see Figure 27).
Set these bits to the charge pump current that the loop filter
is designed with. Best practice is to design the loop filter for a
charge pump current of 2.5 mA or 2.81 mA and then use the
programmable charge pump current to tweak the frequency
response. See the Reference Doubler section for information on
setting the charge pump current when the doubler is enabled.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and fixed modulus values, determines the overall
division ratio from RF
IN
to the PFD input. Bit DB22 sets the
prescaler value.
Operating at CML levels, the prescaler takes the clock from the
RF input stage and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 8 GHz. Therefore,
when operating the ADF4159 at frequencies greater than 8 GHz,
the prescaler must be set to 8/9. The prescaler limits the INT
value as follows:
• Prescaler = 4/5: N
MIN
= 23
• Prescaler = 8/9: N
MIN
= 75
RDIV2
When Bit DB21 is set to 1, a divide-by-2 toggle flip-flop is
inserted between the R counter and the PFD. This feature
can be used to provide a 50% duty cycle signal at the PFD.
Reference Doubler
When Bit DB20 is set to 0, the reference doubler is disabled,
and the REF
IN
signal is fed directly to the 5-bit R counter. When
Bit DB20 is set to 1, the reference doubler is enabled, and the REF
IN
frequency is multiplied by a factor of 2 before the signal is fed into
the 5-bit R counter. When the doubler is disabled, the REF
IN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REF
IN
become active edges at the PFD input.
When the reference doubler is enabled, for optimum phase
noise performance, it is recommended to only use charge pump
current settings 0b0000 to 0b0111, that is, 0.31 mA to 2.5 mA.
In this case, best practice is to design the loop filter to for a
charge pump current of 1.25 mA or 1.57 mA and then use the
programmable charge pump current to tweak the frequency
response.
5-Bit R Counter
The 5-bit R counter (Bits DB[19:15]) allows the input reference
frequency (REF
IN
) to be divided down to supply the reference
clock to the PFD. Division ratios from 1 to 32 are allowed.
12-Bit CLK
1
Divider Value
Bits DB[14:3] program the CLK
1
divider value, which determines
the duration of the time step in ramp mode.