Datasheet

Data Sheet ADF4159
Rev. D | Page 11 of 36
THEORY OF OPERATION
REFERENCE INPUT SECTION
Figure 18 shows the reference input stage. The SW1 and SW2
switches are normally closed (NC in Figure 18). The SW3 switch
is normally open (NO in Figure 18). When power-down is
initiated, SW3 is closed, and SW1 and SW2 are opened. In this
way, no loading of the REF
IN
pin occurs during power-down.
BUFFER
TO R COUNTER
REF
I
N
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
C
ON
T
R
O
L
10849-013
Figure 18. Reference Input Stage
RF INPUT STAGE
Figure 19 shows the RF input stage. The input stage is followed
by a two-stage limiting amplifier to generate the current-mode
logic (CML) clock levels required for the prescaler.
BIAS
GENERATOR
1.6V
AGN
D
AV
DD
2kΩ 2kΩ
RF
IN
B
RF
IN
A
10849-014
Figure 19. RF Input Stage
RF INT DIVIDER
The RF INT CMOS divider allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
VALUE
INT
VALUE
RF INT DIVID
ER N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N COUNTER
10849-015
Figure 20. RF INT Divider
25-BIT FIXED MODULUS
The ADF4159 has a 25-bit fixed modulus. This modulus allows
output frequencies to be spaced with a resolution of
f
RES
= f
PFD
/2
25
(1)
where f
PFD
is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 100 MHz,
frequency steps of 2.98 Hz are possible. Due to the architecture
of the Σ-Δ modulator, there is a fixed +(f
PFD
/2
26
) offset on the
VCO output. To remove this offset, see the Σ-Δ Modulator
Mode section.
INT, FRAC, AND R COUNTER RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the PFD frequency.
The RF VCO frequency (RF
OUT
) equation is
RF
OUT
= (INT + (FRAC/2
25
)) × f
PFD
(2)
where:
RF
OUT
is the output frequency of the external voltage
controlled oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
FRAC is the numerator of the fractional division (0 to (2
25
− 1)).
The PFD frequency (f
PFD
) equation is
f
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (3)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference (R) counter (1 to 32).
T is the REF
IN
divide-by-2 bit (0 or 1).
R COUNTER
The 5-bit R counter allows the input reference frequency (REF
IN
)
to be divided down to supply the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.