Datasheet

ADF4158 Data Sheet
Rev. E | Page 8 of 36
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
PIN 1
INDIC
AT
OR
1
CPGND
NOTES
1. THE LFCS
P HAS
AN EXPOSED P
ADDLE THAT MUST BE CONNECTED T
O GND.
2
AGND
3
AGND
4RF
IN
B
5
RF
IN
A
6A
V
DD
15 D
ATA
16
LE
17
MUXOUT
18
SDV
DD
14 CLK
13 CE
7AV
DD
8AV
DD
9REF
IN
11SDGND
12TX
DATA
10DGND
21
SW2
22
V
P
23
R
SET
24
CP
20
SW1
19
DV
DD
ADF4158
T
OP
VIEW
(Not to Scale)
08728-003
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
4 RF
IN
B Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor,
typically 100 pF.
5 RF
IN
A Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
6, 7, 8 AV
DD
Positive Power Supply for the RF Section. Place decoupling capacitors to the digital ground plane as close as possible
to this pin. AV
DD
must have the same voltage as DV
DD
.
9 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10 DGND Digital Ground.
11 SDGND Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.
12 TX
DATA
Tx Data Pin. Provide data to be transmitted in FSK or PSK mode on this pin.
13 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode.
14 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift
register on the CLK rising edge. This input is a high impedance CMOS input.
15 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high
impedance CMOS input.
16 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the eight latches,
with the latch being selected using the control bits.
17 MUXOUT Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
18 SDV
DD
Power Supply Pin for the Digital Σ-Δ Modulator. This pin should be the same voltage as AV
DD
. Place decoupling
capacitors to the ground plane as close as possible to this pin.
19 DV
DD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close as
possible to this pin. DV
DD
must have the same voltage as AV
DD
.
20 , 21 SW1, SW2 Switches for Fast Lock.
22
V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can be set to
5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
23 R
SET
Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship
between I
CP
and R
SET
is
SET
CPmax
R
I
5.25
=
where:
I
CPmax
= 5 mA.
R
SET
= 5.1 kΩ.
24 CP Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn drives the external VCO.
25 EPAD Exposed Paddle. The LFCSP has an exposed paddle that must be connected to GND.