Datasheet

Data Sheet ADF4158
Rev. E | Page 5 of 36
C Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PN
SYNTH
)
4
−216 dBc/Hz
PLL loop bandwidth = 500 kHz;
measured at 100 kHz offset
Normalized 1/f Noise (PN
1_f
)
5
−110 dBc/Hz 100 kHz offset; normalized to 1 GHz
Phase Noise Performance
6
At VCO output
5805 MHz Output
7
−93 dBc/Hz At 5 kHz offset, 32 MHz PFD frequency
1
Operating temperature for C version: −40°C to +125°C.
2
AC coupling ensures AV
DD
/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(f
PFD
). PN
SYNTH
= PN
TOT
− 10 log(f
PFD
) − 20 log(N).
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
RF
,
and at a frequency offset f is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6
The phase noise is measured with the EVAL-ADF4158EB1Z and the Agilent E5052A phase noise system.
7
f
REFIN
= 128 MHz; f
PFD
= 32 MHz; offset frequency = 5 kHz; RF
OUT
= 5805 MHz; INT = 181; FRAC = 13631488; loop bandwidth = 100 kHz.
TIMING SPECIFICATIONS
AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = SDGND = 0 V; T
A
= T
MIN
to T
MAX
, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter Limit at T
MIN
to T
MAX
(C Version) Unit Test Conditions/Comments
t
1
20 ns min LE setup time
t
2
10 ns min DATA to CLK setup time
t
3
10 ns min DATA to CLK hold time
t
4
25 ns min CLK high duration
t
5
25 ns min CLK low duration
t
6
10 ns min CLK to LE setup time
t
7
20 ns min LE pulse width
Write Timing Diagram
CLK
DATA
LE
LE
DB31 (MSB) DB30
DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
08728-026
Figure 2. Write Timing Diagram